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Patent # Description
US-7,606,157 Apparatus and method for communicating arbitrarily encoded data over a 1-gigabit ethernet
Methods and Systems for transmitting data originating according to a first communications standard over a physical layer using a second communications standard...
US-7,605,854 Operational amplifier for an active pixel sensor
The present invention includes operational amplifier for an active pixel sensor that detects optical energy and generates an analog output that is proportional...
US-7,605,755 Antenna array including virtual antenna elements
A method and associated system for effectively increasing the number of antenna elements within a multi-element antenna system through computation of a response...
US-7,605,734 Digital to analog converter with reduced ringing
Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and...
US-7,605,665 Fractional-N phase locked loop
An apparatus and method is disclosed to substantially reduce phase noise introduced in fractional-N phase-locked loop (PLL) through feedback modulation. A...
US-7,603,506 Motherboard with video data processing card capability
The motherboard comprises a CPU and a memory component; further at least one video data processing chip mounted to the motherboard wherein the video data...
US-7,603,400 Method and system for filter loop with saturation
Methods and systems for processing a signal are disclosed herein and may comprise filtering an input signal and a plurality of saturation limit signals to...
US-7,603,098 Programmable IF frequency filter for enabling a compromise between DC offset rejection and image rejection
The invention enables a compromise between DC offset rejection and image rejection through the use of a bandpass filter having a variable center frequency.
US-7,603,085 Bandpass filter with integrated variable gain function
The invention enables a gain adjustment in a receiver to improve signal quality.
US-7,602,867 System and method for linear distortion estimation by way of equalizer coefficients
Provided is a method and system for estimating distortion in a communications channel including an adaptive equalizer. The method includes determining one or...
US-7,602,839 Chip blanking and processing in SCDMA to mitigate impulse and burst noise and/or distortion
A system for mitigating impairment in a communication system includes a delay block, a signal level block, a moving average window block, an impulse noise...
US-7,602,816 Systems and methods for serial packet synchronization in a voice processing system
A serial packet sync encoder is used to encode a serial packet sync datastream. In an embodiment, the serial packet sync datastream is made up of the packet sync...
US-7,602,815 Using network time protocol in voice over packet transmission
One or more methods and systems of effectively transmitting voice and voice band data from one node to another are presented. In one embodiment, the system...
US-7,602,242 Method and system for polar modulating QAM signals with discontinuous phase
Aspects of a method and system for polar modulating QAM signals with discontinuous phase may include amplifying a signal via a plurality of amplifiers such that...
US-7,600,214 Use of metadata for seamless updates
The invention provides a system and method for updating software in the CPU of a network device without interrupting the operation of the network device. The...
US-7,600,180 Iterative metric updating when decoding LDPC (low density parity check) coded signals and LDPC coded modulation...
Iterative metric updating when decoding LDPC (Low Density Parity Check) coded signals and LDPC coded modulation signals. A novel approach is presented for...
US-7,600,176 Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations...
Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. A means is presented...
US-7,600,131 Distributed processing in a cryptography acceleration chip
Provided is an architecture for a cryptography accelerator chip that allows significant performance improvements over previous prior art designs. In various...
US-7,600,122 Methods and apparatus for accelerating secure session processing
Methods and apparatus are provided for an entity such as a CPU to efficiently call a cryptography accelerator to perform cryptographic operations. A function...
US-7,600,102 Condition bits for controlling branch processing
A processing pipeline with a plurality of pipeline stages is described, with the processing pipeline comprising a front end and a back end. The processing...
US-7,600,057 Method and system for configurable drain mechanism in two-way handshake system
A method and system for configurable drain for two-way handshake system is provided and may comprise coupling a transmitting device to a drain bucket, and...
US-7,599,677 Charge pump circuit having switches
A charge pump circuit that supplies current to an offset current of an output signal for an oscillating circuit is disclosed. The charge pump circuit includes a...
US-7,599,662 Method and system for frequency feedback adjustment in digital receivers
In RF transceivers, a method and a system for a frequency feedback adjustment in digital receivers are provided. A DC offset may result from the difference in...
US-7,599,447 Method and system for a reduced emissions direct drive transmitter for unshielded twisted pair (UTP) applications
In a transmitter that includes a plurality of partitioned DAC processing cells coupled to a corresponding plurality of partitioned encoder processing cells, a...
US-7,599,423 Successive interference canceling for CDMA
Successive interference canceling for CDMA. ICI may result from a signal's multi-path effects, or by filtering/suppression of some of the component energy of the...
US-7,599,369 Apparatus and methods for hardware payload header suppression, expansion, and verification in a DOCSIS network
The present invention provides apparatus and methods for performing payload header suppression (PHS), expansion, and verification in hardware. A PHS verify...
US-7,598,962 Graphics display system with window descriptors
A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video...
US-7,598,813 Radio frequency amplifier with constant gain setting
Radio frequency amplifier with constant gain setting. A circuitry that includes triple well connected MOSFETs is employed to eliminate body effects therein. The...
US-7,598,811 Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain...
Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power...
US-7,598,808 Gigabit ethernet transceiver with analog front end
Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain...
US-7,598,788 Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth
Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth. A novel implementation includes a wideband...
US-7,598,480 Apparatus and method of image processing to avoid image saturation
An imaging device includes a plurality of photo-diodes that operate as optical pixels arranged in a plurality of columns on a single CMOS substrate. The outputs...
US-7,596,669 Apparatus and method for managing memory in a network switch
The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory,...
US-7,596,628 Method and system for transparent TCP offload (TTO) with a user space library
Certain aspects of a method and system for transparent TCP offload with a user space library are disclosed. Aspects of a method may include collecting TCP...
US-7,596,363 Method and system for measuring receiver mixer IQ mismatch
Aspects for measuring receiver mixer IQ mismatch in a transceiver are described. The measuring includes providing a training signal for a receiver mixer, the...
US-7,596,362 DC offset calibration for a radio transceiver mixer
A mixer for a radio transceiver includes a commutating mixer switch having a first differential input port coupled to a DC offset cancellation path. The first...
US-7,596,356 On-chip baseband-to-RF interface and applications thereof
An on-chip baseband-to-RF interface includes a receive/transmit section, a control section, and a clock section. The receive/transmit section, when in a receive...
US-7,596,195 Bandpass filter with reversible IQ polarity to enable a high side or low side injection receiver architecture
The invention enables a reversing IQ polarity in a bandpass filter so that the bandpass filter can filter signals with high side or low side injection.
US-7,596,189 Quadrature receiver sampling architecture
Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I...
US-7,596,148 Receiving data from virtual channels
A method for receiving data from a plurality of virtual channels begins by storing a stream of data as a plurality of data segments, wherein the stream of data...
US-7,596,144 System-on-a-chip (SoC) device with integrated support for ethernet, TCP, iSCSI, RDMA, and network application...
Certain aspects of a method and system for a system-on-a-chip (SoC) device with integrated support for Ethernet, TCP, iSCSI, RDMA, and network application...
US-7,596,137 Packet routing and vectoring based on payload comparison with spatially related templates
An Internet infrastructure with network devices and end point devices containing service module manager and service modules supports packet routing and vectoring...
US-7,595,843 Pulldown field detector
A system and method for detecting the presence and location of pull-down fields in a video field stream. Various aspects of the present invention may comprise...
US-7,595,842 System and method for three dimensional comb filtering
A system and method for determining whether to process a signal using three-dimensional comb filtering. Various aspects of the present invention may comprise...
US-7,595,808 Method and apparatus for updating a color look-up table
Aspects of the invention may include a method updating a color look-up table (CLUT) for a next line of graphics before a current line of graphics has been...
US-7,595,766 Low efficiency integrated circuit antenna
A low efficiency integrated circuit (IC) antenna includes an antenna element and a transmission line. The antenna element is on a first metal layer of a die and...
US-7,595,732 Power generating circuit
A power generating circuit includes a rectifying module and a tuning module. The rectifying module is operably coupled to convert a radio frequency (RF) signal...
US-7,595,704 System and apparatus for a three-line balun with power amplifier bias
A balun that includes a first conductor, a second conductor, and a third conductor. The first conductor has a first length. The first conductor also has a first...
US-7,595,677 Arbitrary clock circuit and applications thereof
A clock circuit includes a waveform generator, a comparison module, and a clock signal module. The waveform generator is coupled to generate a waveform based on...
US-7,595,227 Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the...
Methods for assembling a die-down array integrated circuit (IC) device packages with enhanced thermal, electrical, and input/output properties are presented. The...
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