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Patent # Description
US-7,446,774 Video and graphics system with an integrated system bridge controller
A video and graphics system on an integrated circuit chip includes an integrated system bridge controller to interface a CPU with devices internal to the system...
US-7,446,676 Self-scan programmable keypad interface
Various embodiments are disclosed relating to a self-scan programmable keypad interface. In an example embodiment, an apparatus is provided that includes a...
US-7,446,519 PWM/burst mode switching regulator with automatic mode change
A switching regulator automatically operates in pulse width modulation ("PWM") mode for high load currents and in burst mode for low load currents. The switching...
US-7,444,580 System and method for interleaving data in a communication device
A system and method is provided for interleaving data in a communication device. The system includes a memory that stores blocks of data to be interleaved. A...
US-7,444,455 Integrated gigabit ethernet PCI-X controller
A network controller having a multiprotocol bus interface adapter coupled between a communication network and a computer bus, the adapter including a predictive...
US-7,444,336 Portable media processing unit in a media exchange network
Certain aspects of the invention for porting information between locations in a communication network may comprise storing media along with meta data associated...
US-7,444,165 Method and system for providing broadcast services through a cellular and/or wireless network to a plurality of...
A method and system for communicating information via a plurality of different networks may comprise circuitry in a mobile terminal that receives broadcast...
US-7,444,134 Device and method for transmitting long training sequence for wireless communications
A device and method transmits a frame of a wireless communication. The frame includes a preamble that includes a short training sequence and a long training...
US-7,443,930 Complex digital phase locked loop for use in a demodulator and method of optimal coefficient selection
A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase...
US-7,443,910 PHY control module for a multi-pair gigabit transceiver
A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY...
US-7,443,890 Multi-stage multiplexing chip set having switchable forward/reverse clock relationship
A multi-stage bit stream multiplexer that divides multiplexing functions between two or more integrated circuits. The first integrated circuit receives 16 bit...
US-7,443,812 Voice and data exchange over a packet based network with AGC
A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a...
US-7,443,248 Apparatus and method for phase lock loop gain control using unit current sources
A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel...
US-7,443,221 System and method for fully digital clock divider with non-integer divisor support
A system and method that use a first clock to digitally generate a second clock, wherein the ratio of the frequency of the first clock to the frequency of the...
US-7,443,025 Thermally improved placement of power-dissipating components onto a circuit board
The invention refers to an electronic system, comprising several power-dissipating components, and a circuit board, wherein said power-dissipating components are...
US-7,441,164 Memory bypass with support for path delay test
A method and apparatus are described for testing at least one critical data path in a design of a digital integrated circuit chip during a simulation of the...
US-7,441,098 Conditional execution of instructions in a computer
A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described....
US-7,440,885 Method and system for deterministic control of an emulation
An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event...
US-7,440,777 Multi-transceiver system with MIMO and beam-forming capability
A system and method for communicating with a second communication system utilizing a plurality of antennas. Various aspects of the present invention may comprise...
US-7,440,732 Apparatus and method of local oscillator leakage cancellation
A transmitter includes a first mixer to generate a first output signal by up-converting a first baseband signal having a first DC offset component. A second...
US-7,440,573 Enterprise wireless local area network switching system
A process of controlling a flow of data in a wireless network providing wireless access to the wireless network by wireless devices is disclosed. Data is...
US-7,440,529 Method for synchronization of wireless devices through accelerated advance of counters
A method for synchronizing counters in a wireless terminal device with those of an administrative device. With each increment of the frame counter in a wireless...
US-7,440,521 Method of normalization of forward metric (alpha) and reverse metric (beta) in a map decoder
In a normalization process, overflow occurring in limited size registers, holding the alpha or beta values in a map decoder, may be overcome by subtracting a...
US-7,440,520 System and method for terrestrial high-definition television reception
An adaptive receiver is disclosed for optimally receiving and processing signals. The receiver utilizes one or more memory blocks to store groups of incoming...
US-7,440,504 Method and apparatus for performing deblocking filtering with interlace capability
A method and apparatus are disclosed for adaptively selecting a deblocking filter used in video de-blocking. Determinations are made as to whether each of a set...
US-7,440,469 Descriptor write back delay mechanism to improve performance
A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor write back timer...
US-7,440,416 Hierarchical communication system providing intelligent data, program and processing migration
A hierarchical communication system, arranged in a spanning tree configuration, is described in which wired and wireless communication networks exhibiting...
US-7,440,410 Off-line broadband network interface
A network interface is presented that receives packet data from a shared medium and accomplishes the signal processing required to convert the data packet to...
US-7,440,030 Method and apparatus for interlaced display of progressive video content
A method is provided for displaying progressive video content on an interlaced display device. The method comprises vertically phase shifting video lines of the...
US-7,439,885 Method and system for sample rate conversion
Described herein is a method and system for sampling rate conversion. A clamped cubic spline interpolator (CCSI) may be utilized to interpolate or decimate a...
US-7,439,592 ESD protection for high voltage applications
An ESD device includes a low doped well connected to a first contact and a diffusion area connected to a second contact. A substrate between the low doped well...
US-7,437,583 Method and system for flexible clock gating control
Distributing clock signals within an electronic device may comprise determining a status of at least one gate that controls flow of a clock signal to at least...
US-7,436,902 Multi-dimensional space Gray code maps for multi-dimensional phase modulation as applied to LDPC (Low Density...
Multi-dimensional space Gray code maps for multi-dimensional phase modulation as applied to LDPC (Low Density Parity Check) coded modulation. A novel approach is...
US-7,436,891 Burst mode memory fetches when decoding compressed image data
An image data decompression apparatus for decoding blocks of motion compensated non-intra coded data uses a memory (14) storing reference picture data. A...
US-7,436,882 Decision feedback equalizer and clock and data recovery circuit for high speed applications
A method for communicating data includes equalizing received data to reduce channel related distortion in the received data. A clock having frequency and/or...
US-7,436,617 Controller, state estimator and methods for use therewith
A controller is disclosed that can be used in controlling a drive device of a disk drive, or other systems, in the presence of sinusoidal disturbances. The...
US-7,436,336 Analog digital converter (ADC) having improved stability and signal to noise ratio (SNR)
A sigma delta (.SIGMA..DELTA.) analog to digital converter (ADC) that compensates for the adverse effects associated with the time delay introduced by delay...
US-7,436,253 Method and system for fast calibration to cancel phase feedthrough
Methods and systems for fast calibration to cancel phase feedthrough are disclosed and may comprise individually activating each of n binary-weighted cells...
US-7,434,189 I/O driver power distribution method for reducing silicon area
Embodiments of the present invention provide an integrated circuit (IC) in which power to input output (IO) drivers may be distributed within unused areas over...
US-7,434,134 System and method for trellis decoding in a multi-pair transceiver system
A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional...
US-7,434,065 Secure verification using a set-top-box chip
One or more methods and systems of authenticating or verifying a set-top-box chip in a set-top-box are presented. In one embodiment, a set-top-box incorporates a...
US-7,434,043 Cryptography accelerator data routing unit
Methods and apparatus are provided for handling data at a cryptography accelerator output interface. A shared resource such as a shared output buffer is provided...
US-7,433,697 Synchronized UWB piconets for Simultaneously Operating Piconet performance
Synchronized UWB piconets for SOP (Simultaneously Operating Piconet) performance. A common backbone (either wired or wireless) is employed that provides a common...
US-7,433,662 Mixer gain control with gain tracking offsets
An apparatus and method to use a gain control network across source terminals of cascode transistors that drive a differential current to control gain. The...
US-7,433,660 Iterative multi-stage detection technique for a diversity receiver having multiple antenna elements
An iterative multistage detection system and method for orthogonally multiplexing K channels onto a signal processing chain using N orthogonal sequences of...
US-7,433,659 Iterative multi-stage detection technique for a diversity receiver having multiple antenna elements
An iterative multistage detection system and method for orthogonally multiplexing K channels onto a signal processing chain using N orthogonal sequences of...
US-7,433,656 Reducing flicker noise in two-stage amplifiers
A multi-stage amplifier includes first and second amplification stages and a loading stage, all of which generate flicker noise. A degeneration block is operably...
US-7,433,650 Method of creating incentives for establishing hotspot locations
A process of creating incentives for wireless hotspots by a service provider is disclosed. An access point is provided to a wireless hotspot for wireless devices...
US-7,433,432 Adaptive detector for multiple-data-path systems
An adaptive, reduced-complexity soft-output maximum-likelihood detector that is operable to process data by adaptively selecting a processing scheme based on a...
US-7,433,352 System for the suppression and expansion of packet header information therefor
Data packets transmitted over a cable network are suppressed by hardware at the transmitting end and expanded on the receiving end. This conserves bandwidth as...
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