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Gain insensitive high-pass VGA
An integrated circuit radio transceiver and method therefor includes a high-pass variable gain amplifier (HPVGA) operably disposed within one of the transmitter...
Method and apparatus for high speed signal recovery
A closed-loop circuitry includes, in part, a loop filter and a current source/sink coupled to the loop filter to adjust the phase/frequency of the signal...
Method and system for pattern-independent phase adjustment in a clock and
data recovery (CDR) circuit
Aspects of the pattern-independent phase adjustment system includes a single output data XOR gate coupled to a differential input data signal and a bias voltage...
Computation of decision feedback equalizer coefficients with constrained
feedback tap energy
A Decision Feedback Equalizer (DFE) system includes a DFE and a DFE coefficients processor. The DFE receives an uncompensated signal and operates upon the...
Startup protocol for high throughput communications systems
A startup protocol is provided for use in a communications system having a plurality of transceivers, one transceiver acting as a master and another transceiver...
Redundant radio frequency network having a roaming terminal communication
Disclosed herein is a redundant network and communication protocol at least including host computers, RF base stations, and roaming terminals. The network may...
Self-describing transport protocol segments
Systems and methods that provide self-describing transport protocol segments are provided. In one embodiment, a system that handles transport protocol segments...
Fibre channel arbitrated loop bufferless switch circuitry to increase
bandwidth without significant increase in...
A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each...
System and method for de-interleaving data in a wireless receiver
A system and method for de-interleaving data in a wireless receiver, wherein a single memory buffer is coupled to a read/write unit that performs both first and...
System method and apparatus for a three-line balun with power amplifier
A balun that includes a first conductor, a second conductor and a third conductor. The first conductor has a first length. The first conductor also has a first...
Automatic gain control with three states of operation
A method and apparatus for an automatic gain control circuit (AGC) that utilizes freezing and unfreezing states. A freezing process moves the AGC into a...
Voltage regulator with high voltage protection
A method for regulating a voltage in an integrated circuit device includes providing a first regulated output based upon a first voltage input range and...
Processor sharing technique for communications and other data processing
on a same processor
The computational load imposed by communications software executed on a general purpose processor can be significantly reduced by exploiting periods during an...
LDPC (Low Density Parity Check) coded modulation hybrid decoding using
non-Gray code maps for improved performance
LDPC (Low Density Parity Check) coded modulation hybrid decoding using non-Gray code maps for improved performance. Check node updating and symbol node updating...
IPHD (iterative parallel hybrid decoding) of various MLC (multi-level
IPHD (Iterative Parallel Hybrid Decoding) of various MLC (Multi-Level Code) signals. Various embodiments are provided by which IPHD may be performed on MLC LDPC...
Fast min*- or max*-circuit in LDPC (low density parity check) decoder
Fast min*- (min-star-minus) or max*- (max-star-minus) circuit in LDPC (Low Density Parity Check) decoder. A novel and efficient approach by which certain of the...
Synchronous power gauge
According to one exemplary embodiment, a synchronous power gauge is coupled to a processor for determining total charge consumed from a power source in an...
Modular, portable data processing terminal for use in a radio frequency
Modular, portable data collection terminals are disclosed for use in mixed wireless and hard-wired RF communication networks, wherein various radio transmitter...
Pixel reordering and selection logic
Presented herein are systems and methods for pixel reordering and selection. A decoded frame is stored in a frame buffer with a particular pixel order and byte...
Computation of decision feedback equalizer coefficients with constrained
feedback tap energy
Directly computing Feed Forward Equalizer (FFE) coefficients and Feed Back Equalizer (FBE) coefficients of a Decision Feedback Equalizer (DFE) from a channel...
Hybrid high-speed/low-speed output latch in 10 GBPS interface with half
A high-speed serial demultiplexer receives over four high-speed serial data lines at a nominal rate of 10 GBPS and demultiplexes the data to 16 lines with a rate...
VoIP service threshold determination by home wireless router
A home wireless router establishes a Wireless Local Area Network (WLAN) that supports wireless communications within a WLAN service area. The home wireless...
Integrated user and radio management in a wireless network environment
A system and method in which user management and radio management functionalities associated with a wireless network, such as an IEEE 802.11 wireless network,...
System for mixed analog-digital automatic gain control
Aspects of the invention provide a system for a mixed analog-digital automatic gain control. The received analog signal is amplified by the analog amplifier and...
Apparatus and method to provide a local oscillator signal from a digital
An apparatus provides a local oscillator signal based on a selected channel of an RF input signal. For example, the apparatus can set a frequency of the local...
Low threshold voltage PMOS apparatus and method of fabricating the same
A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For...
Circuit for PLL-based at-speed scan testing
A scheme for PLL-based at-speed scan testing in which a clock generation circuit is used to generate different clock signals to scannable flip-flops of an...
Integrated circuit with DMA module for loading portions of code to a code
memory for execution by a host...
A system, method, and apparatus for dynamically booting processor code memory with a wait instruction is presented herein. A wait instruction precedes the...
Peripheral bus transaction routing using primary and node ID routing
A processing device includes one or more resources, a plurality of peripheral bus interfaces that support resource sharing with a plurality of other processing...
LNA gain adjustment in an RF receiver to compensate for intermodulation
A Radio Frequency (RF) receiver includes a low noise amplifier (LNA) and a mixer coupled to the output of the LNA. The gain of the LNA is adjusted to maximize...
Frequency allocation using a single VCO
An apparatus and method to use a single voltage controlled oscillator (VCO) to generate frequencies to cover multiple frequency bands. The single VCO generates...
Low jitter phase rotator
A phase rotator generates an output signal having plurality of possible output phases with reduced phase jitter. The low jitter phase rotator includes a...
Method and apparatus for performing trellis coded modulation of signals
for transmission on a TDMA channel of a...
A method and apparatus for performing trellis coded modulation of signals for transmission on a TDMA channel of a cable network, such as a DOCSIS cable network,...
Optimal trellis code design for QPSK and higher order quadrature amplitude
A wireless device and system employs a two-dimensional (2-D) Trellis code that can be applied to Quadrature Phase Shift Keying (QPSK) and higher order Quadrature...
Reconstructing a compressed still image by transformation to a compressed
moving picture image
A transcoder (10) and a decoder (80) reconstruct an image from still image compressed data, such as EXIF data. The transcoder transcodes the still image...
Hardware filtering of unsolicited grant service extended headers
A system and method is presented to utilize hardware instead of software to compare for bandwidth request changes between two consecutively received unsolicited...
System and method for scheduling burst profile changes based on minislot
A system and method are presented for changing physical layer (PHY) parameters in a PHY device of a communications system. New parameters are written to a...
Synchronous read channel
A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital...
Low-complexity sampling rate conversion method and apparatus for audio
A low-complexity sampling rate conversion (SRC) method and apparatus for the processing of digital audio signals. A first stage upsamples an input audio signal...
Driver circuit having programmable slew rate
The programmable slew rate driver uses separate and programmably selectable resistors for time constants for on and off transitions on the NMOS and PMOS output...
Battery powered device with dynamic power and performance management
A computing device operates over a range of voltages and frequencies and over a range of processor usage levels. The computing device includes at least a...
Methods and apparatus for performing encryption and authentication
Methods and apparatus are provided for a cryptography accelerator to efficiently perform authentication and encryption operations. A data sequence is received at...
Bandpass filter with integrated variable gain function using improved
The invention enables a gain adjustment in a receiver to improve signal quality by varying resistance of an input resistor array of a bandpass filter, the array...
Methods and circuits for optimal equalization
Methods and circuits utilizing a two stage adaptation algorithm to determine the optimal code for an equalizer to compensate a received signal is disclosed. In...
Method using a one-time programmable memory cell
A one-time programmable device includes a controller, a protection system, a static storage element and a latch, which can be referred to as a latch-based...
Method of and system for performing differential lossless compression
A method of decompressing data words of an instruction set includes: A. filling a primary dictionary with at least one primary data word of the instruction...
Compact bandpass filter for double conversion tuner
A bandpass filter includes a plurality of resonators on a printed circuit board. An input pin is connected to a first resonator of the plurality of resonators....
Method and apparatus for calibrating a phase locked loop in open-loop
Methods and apparatus for calibrating a transitional loop, such as a phase locked loop, are disclosed. An example method includes performing an open loop...
Process monitor for monitoring and compensating circuit performance
A method and system for monitoring and compensating the performance of an operational circuit is provided. The system includes one or more integrated circuit...
Integrated packet bit error rate tester for 10G SERDES
An integrated packet bit error rate tester includes a packet transmit circuit that has a first memory for storing transmit packet data and is connectable to a...