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Patent # Description
US-7,373,116 High output power radio frequency integrated circuit
A high output power radio frequency integrated circuit (RFIC) includes an up-conversion module, a plurality of power amplifier input stages, and a plurality of...
US-7,372,929 Closed loop sub-carrier synchronization system
A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and...
US-7,372,917 Digital algorithm for on-line ACPR optimization in polar RF transmitters
An RF transmitter includes a digital processor that includes a time shift signal determination block that produces a time shift signal based upon a bleed over...
US-7,372,872 System and method for monitoring upstream and downstream transmissions in cable modern system
A network monitor includes means for monitoring downstream traffic from a cable modem termination system (CMTS) to a cable modem (CM), means for monitoring...
US-7,372,839 Global positioning system (GPS) based secure access
Presented herein are systems and methods for global positioning system based secure access. A request for access to a computer network is received. A...
US-7,372,828 Wireless access point management in a campus environment
A Wireless Local Area Network (WLAN) is operated in conjunction with a wired Local Area Network (wired LAN) to service a premises, e.g., a campus setting. The...
US-7,370,265 Bandwidth efficient coded modulation scheme based on MLC (multi-level code) signals having multiple maps
Bandwidth efficient coded modulation scheme based on MLC (Multi-Level Code) signals having multiple maps. The use of multiple maps is adapted to various types of...
US-7,369,816 Highly accurate temperature sensor employing mixed-signal components
A radio transceiver includes circuitry that enables received RF signals to be down-converted to baseband frequencies and baseband signals to be up-converted to...
US-7,369,657 Cryptography accelerator application program interface
Methods and apparatus are provided for making function calls to various cryptography accelerators. An application program interface abstraction layer coupled to...
US-7,369,617 Multi-dimensional data interleaving communications system
An interleaving operation can scramble (permute) a data stream, or each dimension (set of symbols (a, b, c, . . . )) in a data stream, immediately following FEC...
US-7,369,608 Dynamic regulation of power consumption of a high-speed communication system
A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric...
US-7,369,096 Impedance matched passive radio frequency transmit/receive switch
A Radio Frequency (RF) structure services an antenna having a characteristic impedance and includes a differential Power Amplifier (PA), a differential Low Noise...
US-7,369,046 Wireless human interface device with integrated temperature sensor
A wireless human interface device (HID) includes an input interface module for accepting inputs from a user; a microprocessor for processing the accepted inputs;...
US-7,366,940 Multiprotocol computer bus interface adapter and method
A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time...
US-7,366,823 Method and system for memory access
Described herein are a method and system for memory access. As the complexity of digital signal processing applications increases, designs may require multiple...
US-7,366,610 Downloading map segment(s) to a cell phone based upon its GPS coordinates and mobility
A wireless terminal displays its location and navigation information (map segment) on its display. The wireless terminal accesses a Global Positioning System...
US-7,366,486 System and method for coarse/fine PLL adjustment
An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front...
US-7,366,397 V-Chip data processing for decoder with personal video recording functionality
Systems and method for processing v-chip data for an MPEG-2 decoder with personal video recording functionality are provided. In one example, a system that...
US-7,366,300 Methods and apparatus for implementing a cryptography engine
Methods and apparatus are provided for implementing a cryptography engine for cryptography processing. A variety of techniques are described. A cryptography...
US-7,366,258 Chip blanking and processing in SCDMA to mitigate impulse and burst noise and/or distortion
A system for mitigating impairment in a communication system includes a delay block, a signal level block, a moving average window block, an impulse noise...
US-7,366,254 Edge incremental redundancy support in a cellular wireless terminal
A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes a baseband processor, an equalizer, a system processor, and an...
US-7,366,208 Network switch with high-speed serializing/deserializing hazard-free double data rate switch
A network switch for switching packets from a source to a destination includes a source port for receiving an incoming packet from a source, a destination port...
US-7,366,190 Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in...
A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each...
US-7,366,171 Network switch
A network switch for switching packets from a source to a destination includes a source port for receiving an incoming packet from a source, a destination port...
US-7,366,151 Hierarchical data collection network supporting packetized voice communications among wireless terminals and...
A packet-based, hierarchical communication system, arranged in a spanning tree configuration, is described in which wired and wireless communication networks...
US-7,366,092 Hash and route hardware with parallel routing scheme
A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a parallel routing scheme for...
US-7,365,752 Video and graphics system with a single-port RAM
A video and graphics system has an input for receiving compressed video data and an input for receiving graphics data. The compressed video data may include HDTV...
US-7,365,748 Unique method for performing horizontal and vertical video decimation within a wireless device
A method of presenting graphical images within a wireless terminal that includes receiving an original graphical image, having a source resolution, to be...
US-7,365,602 Multilevel power amplifier architecture using multi-tap transformer
A multi-level power amplifier architecture using a multi-tap transformer implemented on a single CMOS integrated circuit wireless communications device is...
US-7,365,548 System and method for measuring on-chip supply noise
A method and system for measuring noise of an on-chip power supply. In an embodiment, the system comprises a delay line that receives as an input a signal such...
US-7,363,575 Method and system for TERC4 decoding using minimum distance rule in high definition multimedia interface (HDMI)...
Certain embodiments of the invention provide a method and system for TERC4 decoding using minimum distance rule. A plurality of bits may be received that may...
US-7,363,557 System for at-speed automated testing of high serial pin count multiple gigabit per second devices
A system performs automated at-speed testing of a plurality of devices that generate serial data signals having multiple gigabit per second baud rates. The...
US-7,363,304 Method and system for providing a hardware sort for a large number of items
A method and system for sorting a number of items in a computer system. The sort is based on a plurality of values of a key. Each item has a value of the...
US-7,362,829 Multi-band single-carrier modulation
Multi-band single-carrier modulation. A novel approach is presented by which interference compensation may be performed for signals received by a piconet...
US-7,362,828 Method of and system for optimizing the capacity of a digital communication system in presence of both internal...
A method of optimizing a communication system for receiving and processing an input communication signal includes selecting a first noise margin m to be applied...
US-7,362,817 UWB (Ultra Wide Band) interference mitigation
UWB (Ultra Wide Band) interference mitigation. A novel solution is presented whereby various piconet operable devices are operated to support a relatively...
US-7,362,797 Physical layer device having an analog SERDES pass through mode
A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion...
US-7,362,769 Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in...
A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each...
US-7,362,694 Programmable identity of I and Q channels
A multiplexing scheme to select either an I component or a Q component for input to I channel and Q channel inputs of a baseband receiver. The selection of which...
US-7,362,384 Apparatus and method for feed-forward image rejection in a dual conversion receiver
A receiver portion includes a bandpass filter (e.g. SAW filter) that performs channel selection from an input signal having a plurality of channels, and an image...
US-7,362,251 Method and system for digital to analog conversion for power amplifier driver amplitude modulation
Aspects of a method and system for digital to analog conversion for power amplifier driver amplitude modulation are presented. Various aspects of the system may...
US-7,362,174 Current-controlled CMOS (C3MOS) wideband input data amplifier for reduced differential and common-mode reflection
Current-controlled CMOS (C3MOS) wideband input data amplifier for reduced differential and common-mode reflection. Impedance matching and bandwidth extension...
US-7,361,540 Method of reducing noise disturbing a signal in an electronic device
Certain aspects of a method for reducing noise disturbing at least one signal in an electronic device may comprise shielding a first layer doped with a first...
US-7,360,146 Inverse function of min*:min*- (inverse function of max*:max*-)
Inverse function of min*:min*- (inverse function of max*:max*-). Two new parameters are employed to provide for much improved decoding processing for codes that...
US-7,360,129 Simultaneous switch test mode
The present invention provides a simultaneous switching (SS) test mode. SS test modules supporting an SS test mode are provided. When SS test mode is enabled, SS...
US-7,360,055 Two address map for transactions between an X-bit processor and a Y-bit wide memory
Presented herein are systems and methods for two address map for transactions between an X-bit processor and a Y-bit wide memory. A processor subsystem comprises...
US-7,360,040 Interleaver for iterative decoder
Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is...
US-7,359,468 Apparatus for synchronizing clock and data between two domains having unknown but coherent phase
A data synchronizer is provided for synchronizing data across two different clock domains in a manner that avoids additive jitter. The data synchronizer includes...
US-7,359,426 Method and system for modulating and demodulating signals in ultra-wide band (UWB) communication systems
In a transceiver system a passband single carrier transmitter is coupled to a first ultra-wide-band wireless transmission channel and a receiver may be coupled...
US-7,359,406 Synchronized transport across non-synchronous networks
A method of providing for synchronizing one or more synchronous terminals with one or more synchronous endpoints, each synchronous terminal and each synchronous...
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