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Patent # Description
US-7,345,490 Filter calibration
A method for calibrating a filter begins with the filter filtering a first signal having a first frequency to produce a first filtered signal, wherein the first...
US-7,343,541 Data integrity in protocol offloading
A method for data verification is provided. An input block of data is received together with a modulo-based input error detection code associated with the input...
US-7,343,472 Processor having a finite field arithmetic unit utilizing an array of multipliers and adders
A processor includes an instruction memory, arithmetic logic unit, finite field arithmetic unit, at least one digital storage device, and an instruction decoder....
US-7,343,456 Load-linked/store conditional mechanism in a CC-NUMA system
A node includes a processor coupled to an interconnect and a memory bridge coupled to the interconnect. The processor is configured to maintain a first...
US-7,343,411 Method and system for secure management and communication utilizing configuration network setup in a WLAN
Methods and systems for enabling communication of information in a secure communication system are disclosed herein and may comprise generating a notification...
US-7,343,177 Modular ear-piece/microphone (headset) operable to service voice activated commands
The present invention provides a modular headset operable to support both voice communications and voice activated commands. This may involve the use of multiple...
US-7,343,160 System and method for servicing communications using both fixed and mobile wireless networks
Mobile wireless device(s) roam within and between premises and a vehicle or other mobile platform and interface to wireless local area networks within the...
US-7,343,144 Frequency synthesizer using PLL architecture for wireless frequency allocation
An apparatus method to provide a frequency synthesizer using a phase locked loop in a communication device to provide a particular frequency allocation to...
US-7,342,979 Incremental redundancy support in a cellular wireless terminal having IR processing module
A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes a baseband processor, an equalizer, a system processor, a...
US-7,342,967 System and method for enhancing performance of personal video recording (PVR) functions on hits digital video...
A system, method, and apparatus for reducing the video decoder processing requirements for rewinding a HITS stream are presented herein. During rewind of a HITS...
US-7,342,956 System and method to extract uplink status flag bits in a cellular wireless network
Determining whether a first wireless terminal may transmit on an uplink to a servicing base station in a cellular wireless communication system includes first...
US-7,342,455 Temperature sensor insensitive to device offsets with independent adjustment of slope and reference temperature
A radio transceiver includes circuitry that enables received RF signals to be down-converted to baseband frequencies and baseband signals to be up-converted to...
US-7,342,428 Pulse-on-edge circuit
A pulse on edge circuit includes a first pull up transistor having its gate terminal coupled to a delayed control signal and a second pull up transistor having...
US-7,341,891 Method for manufacturing a memory cell for modification of revision identifier in an integrated circuit chip
A method for making a memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an...
US-7,340,727 Verilog to C++ language translator
Method and system for translating Verilog to C++ are provided herein. Aspects of the method for translating may include searching for a Verilog pattern in a...
US-7,340,707 Automatic tuning of signal timing
A system and method for automatically tuning timing of a signal (e.g., a data timing signal) utilizing determined delay of a variable delay element and for...
US-7,340,564 Tracing instruction flow in an integrated processor
Tracing instruction flow in an integrated processor by defeaturing a cache hit into a cache miss to allow an instruction fetch to be made visible on a bus, which...
US-7,340,546 Addressing scheme supporting fixed local addressing and variable global addressing
A node comprises one or more resources and a register programmable with an indication during use. The one or more resources are addressed with addresses within a...
US-7,340,220 Phase locked loop with power distribution
A phase locked loop includes a detection module, a control conversion module, a controlled oscillation module, a divider module, and a power distribution module....
US-7,339,986 Method of monitoring the quality of a communications channel
A method is presented that monitors the quality of a communications channel. The method includes receiving a data signal and establishing a zero reference phase...
US-7,339,956 System and method for the synchronization and distribution of telephony timing information in a cable modem network
A method for synchronizing clocks in a packet transport network. The method comprises, receiving an external network clock at a central packet network node and...
US-7,339,941 Connecting ethernet based system on a chip integrated circuits in a ring topology
A plurality of System On a Chip (SOC) integrated circuits, a media that intercouples the plurality of SOC integrated circuits to form at least one SOC LAN ring,...
US-7,339,938 Linked network switch configuration
System and method for integrating communications between two switches. The system includes a first switch, a second switch and a CPU. The first switch has a...
US-7,339,890 Scalable, high-resolution asynchronous transfer mode traffic shaper and method
An ATM network traffic shaper is implemented in hardware. The traffic shaper shapes transmit data on one or more virtual circuits (VCs) according to the...
US-7,339,630 Method and system for a correlation sharpening filter
Methods and systems for correlation sharpening filtering of a composite video signal are provided. A correlation between a current pixel and at least one...
US-7,339,629 Method and system for time constant for a 3D comb filter
Methods and systems for time constant for a 3D comb filter of a video signal are provided. Aspects of the method may include assigning a weight to a 3D comb mesh...
US-7,339,627 Method and system for automatic detection and display of aspect ratio
Certain embodiments of the invention may be found in a method and system for automatic aspect ratio detection and may comprise scanning lines in at least a...
US-7,339,363 Variable gain received signal strength indicator
An RSSI circuit provides a relatively inexpensive technique for accurately measuring received signal strength over a wide dynamic range. A received signal is...
US-7,338,819 System and method for matching chip and package terminals
A system and method for matching chip and package terminals and for packaging integrated circuits. Various aspects of the present invention may comprise...
US-7,337,375 Diagnostics of cable and link performance for a high-speed communication system
A method and system for performing diagnostic tests on a real-time system controlled by a state machine. A sequence of states recorded as the state machine...
US-7,336,939 Integrated tracking filters for direct conversion and low-IF single conversion broadband filters
A radio frequency (RF) tuner includes a programmable tracking filter bank receiving an RF input and outputting a filtered RF signal. A mixer stage receives the...
US-7,336,729 Digital signal processing based de-serializer
A DSP based SERDES performs compensation operations to support high speed de-serialization. A receiver section of the DSP based SERDES includes one or more ADCs...
US-7,336,706 Programmable integrated DiSEqC transceiver
Programmable integrated Digital Satellite Equipment Control (DiSEqC) transceiver. The DiSEqC functionality is integrated onto a semiconductor device. Rather than...
US-7,336,287 Video and graphics system with square graphics pixels
A video and graphics system provides square graphics pixels to blend images having 640.times.480 pixels, such as graphics images provided by some set top boxes...
US-7,336,131 Gigabit ethernet transceiver with analog front end
Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain...
US-7,336,129 Analog amplitude detector
A circuit includes at least two transistors arranged to form a current mirror, at least two transistors operatively coupled to the current mirror, where the...
US-7,334,253 Method and apparatus for detection and classification of impairments on an RF modulated network
A method is disclosed for maintaining the integrity of a communication system. The method comprises detecting common path distortion (CPD) and periodic...
US-7,334,200 Low-error fixed-width modified booth multiplier
A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth...
US-7,334,179 Method and system for detecting and correcting errors while accessing memory devices in microprocessor systems
A method and system for ensuring data integrity in a data processing system may comprise monitoring when data for a specified device is available for error...
US-7,334,153 Low-speed DLL employing a digital phase interpolator based upon a high-speed clock
A low-speed delay locked loop (DLL) facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific...
US-7,334,074 Method and system for multi-channel transfer of data and control
A system and method for transferring information in a multi-channel, point-to-point environment are described. In one embodiment, a number of processing chips...
US-7,334,068 Physical layer device having a SERDES pass through mode
A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second...
US-7,333,790 Method and apparatus for generating arbitrary phase shift using a phase shifter based on adding two...
A radio frequency (RF) phase shifter having an RC-CR circuit that includes a first capacitor having a first capacitor node and a second capacitor node and a...
US-7,333,714 Method and system for performing reverse play of SD MPEG video
One or more methods and systems to efficiently process MPEG video in order to perform a reverse play or slow rewind function are presented. The method reduces...
US-7,333,580 Pipelined parallel processing of feedback loops in a digital circuit
Digital circuits and methods for designing digital circuits are presented. In an embodiment, a number of bits (B) of a bit-stream to be processed in parallel by...
US-7,333,537 System for monitoring the quality of a communications channel with mirror receivers
A system is presented that monitors the quality of a communications channel with mirror receivers. A first receiver and a second receiver, coupled in parallel...
US-7,333,513 Method, system, and computer program product for synchronizing voice traffic with minimum latency
A supervisory communications node monitors and controls communications with a plurality of remote devices throughout a widely distributed network. A method,...
US-7,333,495 Method for scheduling upstream communications
A system and method is provided for scheduling transmissions from a plurality of services operating over a widely distributed communications network. A headend...
US-7,333,476 System and method for operating a packet voice far-end echo cancellation system
A packet voice transceiver adapted to reside at a first end of a communication network and to send an ingress communication signal comprising voice packets to,...
US-7,333,475 Switchboard for multiple data rate communication system
A switchboard device and methods of operation of same are disclosed. Embodiments of the invention may provide a flexible means of interconnecting wideband and...
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