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Wireless terminal operations within wireless local area network
A wireless terminal operates within a Wireless Local Area Network (WLAN) and includes a directional antenna, a radio frequency unit operably coupled to the...
Packet voice system with far-end echo cancellation
A packet voice transceiver adapted to reside at a first end of a communication network and to send and receive voice packets to and from a second packet voice...
Phase controlled high speed interfaces
A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased...
Active pixel array with matching analog-to-digital converters for image
An imaging device includes a plurality of photo-diodes arranged in a plurality of columns on a single Complementary Metal Oxide Semiconductor (CMOS) substrate. A...
Method and system for improved lookup table (LUT) mechanism for Huffman
Methods and systems for improved lookup table mechanism for Huffman decoding are provided and may include selecting, based on a plurality of entropy encoded bits...
Cell phone wireless speaker-microphone sleep modes
A hand held radio host includes circuitry for selectively providing power to radiating transceiver elements and non-radiating application elements according to a...
Transceiver for bidirectional frequency division multiplexed transmission
The present invention relates to a transceiver for bidirectional frequency division multiplexed transmission, a communication system including one or more...
Reduced size and power demapper for viterbi decoding
A Viterbi decoding demapping scheme for a wireless communications device processor substantially implemented on a single CMOS integrated circuit is described. By...
Using clock and data recovery phase adjust to set loop delay of a decision
In a method and apparatus for communicating data, a decision feedback equalizer equalizes received data to reduce channel related distortion in the received...
Orthogonal normalization for a radio frequency integrated circuit
A radio frequency integrated circuit includes a transmitter section, and a receiver section. The receiver section includes a low noise amplifier, down conversion...
Metal-insulator-metal (MIM) capacitor
A metal-insulator-metal (MIM) capacitor is made according to a copper dual-damascene process. A first copper or copper alloy metal layer if formed on a...
RFIC die and package
A radio frequency integrated circuit (RFIC) includes a die and a package. The die includes a radio frequency (RF) input/output (I/O) section, an RF to baseband...
Low density parity check (LDPC) code decoder using min*, min**, max* or
max** and their respective inverses
Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated...
Method and apparatus for selectively deskewing data traveling through a
A method for selectively deskewing data traveling through a bus in a network device is disclosed. Bit-level data is received from each data line of a plurality...
Phase detectors in carrier recovery for offset QAM and VSB
A carrier recovery, symbol timing, and carrier phase tracking systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system....
Channel equalization with SCDMA modulation
The present invention relates a system and method for mitigating impairment in a communication system. In one embodiment, the system includes a transmitter...
Home phone line networking next generation enhancements
New version devices of a home phone line network may operate on a first carrier frequency (within the new version frequency band) while old version devices may...
Method and system for a polyphase clock for a second intermediate
frequency (IF) mixer to improve signal quality
Methods and systems for reducing interference in a signal are disclosed herein. Aspects of the method may comprise generating a first local oscillator signal....
Low OHMIC layout technique for MOS transistors
A method of making a transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first and...
Via providing multiple electrically conductive paths
A via provides a plurality of electrical connections between conductors on different layers of a circuit board. The via includes an opening through the circuit...
Phase adjust using relative error
A system may adjust the times at which data is sampled by separate sampling mechanisms. Here, it may be desirable to ensure that one sampler samples data at...
Instruction sequence verification to protect secured data
Intended for an information security application, particularly in networked information systems, the present invention includes two methods and systems for...
System and method of utilizing off-chip memory
One or more methods and/or systems of utilizing a memory external to an integrated circuit chip are presented. In one embodiment, the system comprises an...
Method for packet loss and/or frame erasure concealment in a voice
A method for performing packet loss concealment (PLC) and/or frame erasure concealment (FEC) in a speech decoder of a voice communication system. In accordance...
Method and system for a mobile architecture that supports a cellular or
wireless network and broadcast...
In an RF communication system, aspects for supporting cellular or wireless network and broadcast utilizing an integrated single chip cellular and broadcast...
PLL frequency synthesizer architecture for low phase noise and reference
A frequency synthesizer for use in a transceiver generates a relatively high reference frequency with fine frequency resolution and low in-band phase noise by...
Transmit power control of wireless communication devices
A method and apparatus for controlling transmit power of a wireless communication device includes processing that begins when a transmitting wireless...
Transceiver system and method supporting variable rates and multiple
Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device...
IP multicast packet replication process for 4K VLANS
A network device for controlling data flow can have a buffer configured to receive a packet, a first determining unit configured to determine a multicast group...
Efficient optimization algorithm in memory utilization for network
A communication device configured to assign a data packet to a memory bank of a memory device is provided. The communication device includes an input port for...
System and method for medium access control in a power-save network
A method and apparatus for accessing, controlling and utilizing a network communication medium. Various aspects of the present invention may comprise a first...
Subranging analog to digital converter with multi-phase clock timing
An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a...
LDPC (Low Density Parity Check) coded modulation symbol decoding using
non-Gray code maps for improved performance
LDPC (Low Density Parity Check) coded modulation symbol decoding using non-Gray code maps for improved performance. Symbol decoding is supported by appropriately...
Method and apparatus for efficient matrix multiplication in a direct
sequence CDMA system
A system and method are disclosed for efficiently performing multiplication of an input vector and an input matrix having a limited number of possible values for...
Dual-mode clock for improved power management in a wireless device
A dual mode clock for providing first and second clock signals to a wireless interface unit. The first and second clock signals correspond to first and second...
Determination of variable code rates for a rate control sequence
Determination of variable code rates for a rate control sequence. A rate control sequence governs symbols that are to be encoded and/or decoded. A different rate...
Method and system for providing zero detect and auto-mute
Provided is a system and method for muting zero level pulse code modulated (PCM) samples. PCM samples are received as inputs to a digital to analog converter...
Apparatus for, and method of, processing signals transmitted over a local
An aspect of the invention provides for recovering communicated information in a communication system. Recovering communicated information in a communication...
Bit stream conditioning circuit having adjustable PLL bandwidth
A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a...
Off-chip LC circuit for lowest ground and VDD impedance for power
Off-chip LC circuit for lowest ground and VDD impedance for power amplifier. A novel approach is made by which a chip to PCB (Printer Circuit Board) interface...
Phase adjustment method and circuit for DLL-based serial data link
A delay locked loop circuit with a first flip flop driven by a 0.degree. clock and receiving the input data. A second flip flop by a 180.degree. clock and...
Apparatus and method to switch a FIFO between strobe sources
A first-in, first-out (FIFO) unit switches between strobe sources. The FIFO uses a multiplexer to switch between two or more strobes so that different data...
System on a chip for caching of data packets based on a cache miss/hit and
a state of a control signal
A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated...
Application based adaptive encoding
A system and method for encoding dynamic image information for an image generated by a computer application executing on a processor. Various aspects of the...
High precision continuous time g.sub.mC BPF tuning
High precision continuous time g.sub.mC BPF (Band Pass Filter) tuning. A novel approach is presented by which a continuous time signal serves as a BPF control...
Symmetrical clock distribution in multi-stage high speed data conversion
The present invention provides a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data...
Apparatus and method to receive and decode incoming data and to handle
repeated simultaneous small fragments
A data aligner aligns a data segment having a granularity of less than a width of an internal data path. The data aligner aligns a fragment of data for alignment...
Open loop subcarrier synchronization system
A system and method for synchronizing signals having respective sub-carriers in a signal processing system. Various aspects of the present invention may comprise...
Delay generator with symmetric signal paths
A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay...
System and method for task arbitration in multi-threaded simulations
Present herein is a system and method for arbitration in multi-threaded programming. Task calls are directed to a task wrapper that associates the task call with...