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Patent # Description
US-7,305,036 System and method for entropy code preprocessing
A system and method for preprocessing a bitstream of compressed video data is presented herein. The bitstream of compressed video data can include, for example,...
US-7,305,029 Multi-pair gigabit ethernet transceiver
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver...
US-7,305,007 Receiver-aided set-up request routing
Systems and methods that provide receiver-aided set-up request routing are provided. In one embodiment, an incoming packet is received and parsed. A probability...
US-7,304,992 Fast flexible filter processor based on range checking and a method of processing based thereon
A network component for processing a packet can include a rules table configured to have a plurality of entries, and sets of first storage units within each one...
US-7,304,652 System and method for providing graphics using graphical engine
Systems and methods that provide graphics using a graphical engine are provided. In one example, a system may provide layered graphics in a video environment....
US-7,304,538 Accurate quiescent current control scheme in floating controlled class AB amplifier
Provided is an amplifier including a system for controlling output stage quiescent current. The amplifier includes a driving stage including first pmos and nmos...
US-7,302,545 Method and system for fast data access using a memory array
First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits....
US-7,302,521 Method and computer program product for combining resources of multiple BIOS ROMS and managing them as a single...
A method and related computer program product for combining resources of multiple RAID controllers and managing them as a single entity, comprising searching the...
US-7,302,505 Receiver multi-protocol interface and applications thereof
A receiver multi-protocol interface includes a wide bandwidth amplifier, a data sampling module, and a clocking module. The wide bandwidth amplifier amplifies a...
US-7,302,503 Memory access engine having multi-level command structure
A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue...
US-7,302,013 Multi-mode variable rate digital satellite receiver
Digital signal processing for television signals includes digital feedback loops. Analog information signals are oversampled to provide digital signals. The...
US-7,301,993 Channel estimation in a spread spectrum receiver
A method and apparatus for channel estimation in a spread spectrum receiver include processing that begins by despreading a received spread spectrum complex...
US-7,301,902 Generic on-chip homing and resident, real-time bit exact tests
Details of media encoding and decoding devices which support generic homing sequences, and methods for operating such devices are disclosed. The use of generic...
US-7,301,582 Line address computer for providing line addresses in multiple contexts for interlaced to progressive conversion
Presented herein is a system and method for a line address computer for providing line addresses in multiple contexts for interlaced to progressive conversion. A...
US-7,301,394 Impedance matched variable gain low noise amplifier using shunt feed-back
The variable gain amplifier includes a forward path that provides the amplifier variable gain, and a feedback path. The feedback path uses a switch that is...
US-7,301,365 On-chip source termination in communication systems
A communication system includes an integrated circuit (IC) die having an on-chip source termination. The on-chip source termination can be a non-precision...
US-7,299,355 Fast SHA1 implementation
Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which SHA1 multi-loop and/or multi-round...
US-7,299,306 Dual numerically controlled delay logic for DQS gating
Presented herein is a scheme for reducing the likelihood of erroneous DQS signals. Logic is incorporated proximate to a memory controller and receives a signal...
US-7,299,070 Dynamic MIMO resource allocation during a single communication
A system and method for providing dynamic allocation of MIMO communication resources during a single communication. Various aspects of the present invention may...
US-7,299,006 Adaptive radio transceiver
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local...
US-7,298,705 Fast-path implementation for a double tagging loopback engine
A network component for processing a packet can include a buffer configured to receive a packet, a forwarding unit configured to forward the packet received at...
US-7,298,418 Method and system for processing in a non-line locked system
Certain embodiments of the invention disclose a method and system for processing in a non-line locked system. The phase relationship between the sub-carrier...
US-7,298,301 Synchronous data serialization circuit
In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first...
US-7,296,295 Media processing system supporting different media formats via server-based transcoding
Systems and methods that reformat media are described. In one embodiment, a system may include, for example, a server, a first communications device and a second...
US-7,296,216 Stopping and/or reducing oscillations in low density parity check (LDPC) decoding
Stopping or reducing oscillations in Low Density Parity Check (LDPC) codes. A novel solution is presented that completely eliminates and/or substantially reduces...
US-7,296,174 Apparatus and method to interface two different clock domains
A gearbox is placed between two clock domains to allow data to be transferred from one domain to the other. Although the two domains may operate at the same...
US-7,296,141 Method for cancelling speculative conditional delay slot instructions
A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot...
US-7,296,086 Multiple mode of operation handshaking between DSL modems
A method for handshaking between DSL modems begins when a central office DSL modem transmits an initiation signal that utilizes a pattern of symbol times to...
US-7,295,949 Energy efficient achievement of integrated circuit performance goals
A system and method for meeting performance goals in an electronic system in an energy efficient manner. Various aspects of the present invention may comprise...
US-7,295,637 Method and apparatus for diversity combining and co-channel interference suppression
A method and apparatus for controlling an antenna array for wireless communication are described. The method uses the statistical characteristics of the received...
US-7,295,607 Method and system for receiving pulse width keyed signals
Provided is a method to process a pulse width coded signal. the method includes digitizing a received pulse width coded signal and transforming the digitized...
US-7,295,555 System and method for identifying upper layer protocol message boundaries
Systems and methods that identify the Upper Layer Protocol (ULP) message boundaries are provided. In one example, a method that identifies ULP message boundaries...
US-7,295,552 Cluster switching architecture
A network switch including at least one data port interface supporting a plurality of data ports, at least one stack link interface configured to transmit data...
US-7,295,528 Peer to peer wireless communication conflict resolution
A method for use by one peer of peer wireless interfaces devices of a wireless communication device to cooperatively provide wireless communications in a...
US-7,295,397 Feedforward controller and methods for use therewith
A controller includes a combining module that generates a total control signal for the drive device of a disk drive by combining a feedback control signal and a...
US-7,295,250 Apparatus and method for restoring DC spectrum for analog television reception using direct conversion turners
A DC compensation circuit restores the frequency spectrum of an input signal at DC (or 0 Hz) by removing or reducing DC offset, 1/f noise, or any other unwanted...
US-7,295,059 System and method for common mode bias for high frequency buffers
Methods and systems for reducing parasitic capacitance of a buffer for an electric circuit are disclosed herein. Aspects of the method may comprise coupling a...
US-7,293,214 Testable design methodology for clock domain crossing
A design methodology to debug synchronization of a signal crossing clock domains. A testable synchronization control logic utilizes a programmable register to...
US-7,292,102 Gain control scheme independent of process, voltage and temperature
An apparatus and method to use a shunt network across source terminals of cascode transistors that drive a differential current to control gain. When the gates...
US-7,292,101 Digitally adjustable variable gain amplifier (VGA) using switchable differential pairs
A variable gain amplifier including a stage. The stage having a set of switchable differential pairs. The stage providing a gain range to a signal and adjusting...
US-7,292,072 Sub-micron high input voltage tolerant input output (I/O) circuit
A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the...
US-7,290,134 Encapsulation mechanism for packet processing
Systems and methods are disclosed for processing data packets. Such a system may generate a header for a session and repeatedly use that header to generate...
US-7,289,813 Using signal-generated location information to identify and list available devices
A signal-generated locator for locating at least one device can include a transmitter configured to transmit at least one first signal and a receiver configured...
US-7,289,791 Methods of recording voice signals in a mobile set
The present invention relates to a mobile set integrating a memory efficient data storage system for the real time recording of voice conversations, data...
US-7,289,782 Linearized fractional-N synthesizer having a gated offset
A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a...
US-7,289,632 System and method for distributed security
A security architecture in which a security module is integrated in a client machine, wherein the client machine includes a local host that is untrusted. The...
US-7,289,543 System and method for testing the operation of a DLL-based interface
A high-speed bit stream data conversion circuit receives a first bit stream(s) and recovers a clock signal from the first bit stream(s). The data conversion...
US-7,288,990 Reference buffer with dynamic current control
A method can allow a system to selectively control increasing of a bias source in a reference buffer or decreasing impedance looking into a output of the...
US-7,287,649 System on a chip for packet processing
A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated...
US-7,287,212 Methods and systems for Viterbi decoding
An execution unit and method for performing Viterbi decoding is provided. The instruction may be built into an execution unit which executes other instructions,...
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