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Patent # Description
US-7,287,152 Conditional execution per lane
A computer system for conditionally performing an operation defined in a computer instruction, an execution unit of the computer system comprises at least one...
US-7,286,811 Local oscillator apparatus and method
A direct conversion satellite tuner is fully integrated on a common substrate. The integrated tuner receives an RF signal having a plurality of channels and...
US-7,286,794 Method and system for joint broadcast receiving and cellular communication at mobile terminal or device without...
Methods and systems for communicating information via a plurality of different networks are disclosed herein. Aspects of the method may comprise receiving...
US-7,286,622 System and method for performing on-chip synchronization of system signals utilizing off-chip harmonic signal
Aspects of the invention provide a method end system for reducing signal distortion within an on-chip transceiver module. In response to receipt of a signal...
US-7,286,597 Methods and systems for adaptive receiver equalization
Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the...
US-7,286,547 Dynamic adjust multicast drop threshold to provide fair handling between multicast and unicast frames
A network device for managing data flow can have a data port configured to receive data, a plurality of pointers for pointing to the data received, and a queue...
US-7,285,993 Method and system for a divide by N circuit with dummy load for multiband radios
Certain embodiments of the invention provide a method and system for symmetrically loading a divider circuit for multiband receivers. The method may comprise...
US-7,284,266 System and method for secure biometric identification
A system and method for secure biometric identification. The inventive system includes a mobile unit and a server. The mobile unit is adapted to receive...
US-7,284,076 Dynamically shared memory
A method and a system for allocating memory in a memory buffer that is part of a data distribution device. Generally, the allocation of memory is for the purpose...
US-7,284,072 DMA engine for fetching words in reverse order
Presented herein is a direct memory access engine for providing data words in the reverse order. The data words are fetched in batches comprising a predetermined...
US-7,283,803 Location-aware application based quality of service (QOS) via a broadband access gateway
A system and method supporting access to multimedia information based upon user-defined quality of service criteria is disclosed. A broadband access gateway may...
US-7,283,800 Adaptive mixer output filter bandwidth control for variable conversion gain down-conversion mixer
An improved adaptive mixer for use in the down conversion module of a wireless transceiver. The adaptive mixer comprises a conversion gain module that is...
US-7,283,793 Package filter and combiner network
A transceiver front end circuit includes an antenna terminal capable of being coupled to an antenna. A first balun circuit has a single input that is coupled to...
US-7,283,585 Multiple data rate communication system
Seamless wideband support is afforded by utilizing split-band data streams. For wideband signals, the 8 kHz bandwidth is divided into a low band, with...
US-7,283,481 Auto detection of copper and fiber mode
Methods and systems for operating a physical layer device ("PHY") in an Ethernet network include methods and systems for detecting active link partners and for...
US-7,283,176 Method and system for detecting field ID
Methods and systems for determining fields in a video signal are disclosed. Historic field ID values for a received video signal may be stored and subsequently...
US-7,282,994 Active load with adjustable common-mode level
A differential preamplifier includes an active load with adjustable common-mode output level. The active load includes a transistor pair, a resistor pair, and a...
US-7,282,991 On-chip amplifier/line driver compensation circuit
An embodiment of the present invention includes an amplifier on an integrated circuit, with the amplifier having positive and negative inputs, and positive and...
US-7,281,192 LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node...
LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing. This novel approach to decoding of LDPC...
US-7,281,069 Method and system for extending the functionality of an embedded USB transceiver interface to handle threshold...
Methods and systems for extending the functionality of an embedded Universal Serial Bus (USB) transceiver interface to handle threshold shift of a USB 2.0 bus...
US-7,280,541 Packet filtering based on conditional expression table
A filter for processing a packet can have a plurality of first masks for masking the packet, and a storage unit configured to correspond to the plurality of...
US-7,280,155 Method and system for converting interlaced formatted video to progressive scan video
Processing video signals may comprise converting interlaced formatted video to progressive scan video by simultaneously performing: color edge detection on a...
US-7,278,079 Test head utilized in a test system to perform automated at-speed testing of multiple gigabit per second high...
A portion of a test head utilized to perform simultaneous automated at-speed testing of a plurality of devices that generate serial data signals having gigabit...
US-7,277,860 Mechanism for using clamping and offset techniques to adjust the spectral and wideband gains in the feedback...
An integrated digital BTSC encoder substantially implemented on a single CMOS integrated circuit is described. By saturating and adding offsets to the value of...
US-7,277,688 DC offset correction for very low intermediate frequency receiver
A wireless receiver includes a local oscillator, a mixer, a band pass filter, a DC offset determination module, a DC offset correction module, a subtraction...
US-7,277,542 Stream cipher encryption application accelerator and methods thereof
A system for encrypting and decrypting data formed of a number of bytes using the ARCFOUR encryption algorithm is disclosed. The system includes a system bus and...
US-7,277,506 Maximum likelihood sequence estimator which computes branch metrics in real time
An improved method and apparatus for Viterbi Algorithm calculations for maximum likelihood sequence estimators in communication receivers is disclosed. The...
US-7,277,481 Technique for minimizing decision feedback equalizer wordlength in the presence of a DC component
A system for reducing the complexity of an adaptive decision feedback equalizer, for use in connection with a dual-mode QAM/VSB receiver system is disclosed. QAM...
US-7,277,438 Fast flexible range checking
A network component for processing a packet can include at least one first storage unit configured to store a packet field value within the packet, at least one...
US-7,277,420 Temporal alignment of codec data with wireless local area network RF slots
A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other WLAN device. The WLAN...
US-7,277,417 Low power protocol for wireless terminal peer-to-peer communications
A Wireless Local Area Network (WLAN) system in which wireless terminals each operate upon battery power. One of the wireless terminals acts as a Master to...
US-7,277,409 Wireless local area network management
Wireless local area network (WLAN) management. A novel approach is provided to associate various wireless stations (STAs) to the WLAN via appropriately selected...
US-7,277,100 Managing multi-component data
Multi-component data is managed. Pixel image data is stored in a machine readable memory device. The pixel image data is decomposed into multiple colorspace...
US-7,277,099 Video and graphics system with an MPEG video decoder for concurrent multi-row decoding
A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV...
US-7,276,970 System and method for linearizing a CMOS differential pair
An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides...
US-7,275,115 Cable modem system and method for supporting packet PDU compression
A cable modem system and method are provided for using a data compression dictionary to transmit compressed payload data in a DOCSIS network while utilizing...
US-7,274,915 Low-noise transmitter system and method
A low-noise transmitter architecture and method for high linearity, high output-swing systems such as Asymmetrical Digital Subscriber Line (ADSL) systems. The...
US-7,274,913 Transceiver system and method of using same
A chip comprises and operational section and an input/output section. The operational section includes a controller. The input/output (I/O) section is coupled to...
US-7,274,792 Methods and apparatus for initialization vector processing
Methods and apparatus are provided for using explicit initialization vectors in both encryption and decryption processing. In one example, a sender generates an...
US-7,274,705 Method and apparatus for reducing clock speed and power consumption
A system for reducing clock speed and power consumption in a network chip. The system has a core that transmits and receives signals at a first clock speed. A...
US-7,274,698 Multilevel parser for conditional flow detection in a network device
A process of filtering packet data in a network device is disclosed. A descriptor table is accessed to obtain a first descriptor and a first field is extracted...
US-7,274,588 Compact and highly efficient DRAM cell
A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing,...
US-7,274,403 Motion adaptive deinterlacer with integrated dynamic format change filter
A system and method that scales interlaced video fields with different sizes in a deinterlacer. The deinterlacer may expect video fields of a certain size. The...
US-7,274,315 Scrambled block encoder
A block encoder flexibly encodes K codes to produce an encoded data block. The block encoder receives an unformatted block of 10 Gigabit Media Independent...
US-7,274,260 Methods and systems to provide a plurality of signals having respective different phases
A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input...
US-7,274,253 Transmitter apparatus with extended gain control
A transmitter includes a first variable gain amplifier (VGA) and a second VGA coupled to an output of the first VGA. The first and second VGAs each comprise a...
US-7,273,391 Apparatus for improved connector layout
A board has connectors for interfacing to external devices mounted at a rearward edge of the board, minimizing the need to make connections and route connecting...
US-7,272,804 Generation of RTL to carry out parallel arithmetic operations
Computer-implemented method and system for generating an optimized description of an arithmetic function comprising at least two of an addition, a...
US-7,272,769 System and method for interleaving data in a wireless transmitter
A system and method for interleaving data in a wireless transmitter wherein bits from the input data stream are sent to downstream processing without being...
US-7,272,768 Edge incremental redundancy memory structure and memory management
A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes at least one processing device, an IR processing function, and...
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