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Patent # Description
US-7,260,166 Systems for synchronizing resets in multi-clock frequency applications
Methods and systems for synchronizing a reset signal with a local clock that drives a circuit. In the circuit, the reset signal can be used to reset one or more...
US-7,260,165 Method for synchronization through accelerated advance of counters
A method for synchronizing counters in a terminal device, such as a cable modem in a DOCSIS-based system, with those of an administrative device, such as a...
US-7,260,119 System, method, and computer program product for ethernet-passive optical networks
A system, method, and computer program product for synchronizing time between a centralized controller device and at least one subscriber device on an Ethernet...
US-7,260,020 Synchronous global controller for enhanced pipelining
The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and...
US-7,259,956 Scalable integrated circuit high density capacitors
The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example,...
US-7,259,626 Apparatus and method for biasing cascode devices in a differential pair using the input, output, or other nodes...
A differential amplifier is configured in a cascode configuration that includes input transistors that are connected to corresponding cascode transistors. The...
US-7,259,457 Die-up ball grid array package including a substrate capable of mounting an integrated circuit die and method...
An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate...
US-7,259,448 Die-up ball grid array package with a heat spreader and method for making the same
An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate...
US-7,257,764 FEC (Forward Error Correction) decoder with dynamic parameters
FEC (Forward Error Correction) decoder with dynamic parameters. A novel means by which FEC parameters may be encoded into, and subsequently extracted from, a...
US-7,257,549 Systems and circuits for providing support for user transactions on a media exchange network
A system providing support for user transactions in a media exchange network is disclosed. An embodiment of the present invention may comprise a television...
US-7,257,383 Method and system for improving dynamic range for communication systems using upstream analog information
The receiver is provided which comprises a mixer, a low pass filter coupled to the mixer and a plurality of gain controllers serially coupled to an output of the...
US-7,257,380 Integrated multimode radio and components thereof
An integrated multimode radio includes a multimode receiver and a multimode transmitter. The multimode receiver includes a shared receiver front-end, a receiver...
US-7,257,154 Multiple high-speed bit stream interface circuit
A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a...
US-7,257,102 Carrier frequency offset estimation from preamble symbols
Carrier frequency offset (CFO) estimation from preamble symbols. Any communication receiver may be adapted to perform the CFO estimation. The CFO estimation is...
US-7,256,790 Video and graphics system with MPEG specific data transfer commands
A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data...
US-7,256,725 Resistor ladder interpolation for subranging ADC
An analog to digital converter includes a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a...
US-7,254,768 Memory command unit throttle and error recovery
A network device for minimizing latency and correcting errors associated with information transmitted from an external memory device. The network device includes...
US-7,254,495 System and method for detecting a device requiring power
A system and technique for detecting a device that requires power is implemented with a power detection station. The power detection system includes a detector...
US-7,254,396 Network or access point handoff based upon historical pathway
A device for handing off a wireless connection can include a receiver configured to receive a communication signal from a wireless device within a first wireless...
US-7,254,190 Satellite receiver
Systems and techniques for receiving a satellite signal wherein the signal is demodulated and iterative decoded. It is emphasized that this abstract is provided...
US-7,254,183 Dual link DVI transmitter serviced by single phase locked loop
A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) to service both a primary link and a secondary...
US-7,254,167 Constellation-multiplexed transmitter and receiver
A device of dynamic communication of information allows, on the average, non-integer bits per symbol transmission, using a compact code set or a partial response...
US-7,254,164 Method for transconductance linearization for DC-coupled applications
A Class AB voltage-to-current converter includes a plurality of DC coupled transconductance stages that produce a linearized output and a biasing circuit. The...
US-7,254,120 Data rate controller
The present invention provides a data rate controller system for determining the coder used, and hence the data rate, for a plurality of channels in an...
US-7,254,116 Method and apparatus for transceiver noise reduction in a frame-based communications network
A method of and apparatus for noise reduction for a transceiver transmitting frames over a transmission medium in a frame-based communications network. A...
US-7,253,763 Switching between lower and higher power modes in an ADC for lower/higher precision operations
An analog-to-digital converter (ADC) disposed in a data reception path to convert data from an analog format to a digital format is switched between two or more...
US-7,253,753 Method and apparatus of performing sample rate conversion of a multi-channel audio signal
A method and apparatus are disclosed for performing sampling rate conversion of an audio signal from a first sampling rate to any of a plurality of higher...
US-7,251,759 Method and apparatus to compare pointers associated with asynchronous clock domains
A multi-bit write pointer that is associated with a first clock can be converted to a single-bit write pointer. A multi-bit read pointer that is associated with...
US-7,251,297 Method and system to identify and characterize nonlinearities in optical communications channels
A method for identifying and modeling nonlinearities in communications channels, particularly optical communication channels. A channel in general is modeled as...
US-7,251,217 Load balancing in link aggregation and trunking
A communications network switch includes a plurality of network ports for transmitting and receiving packets to and from network nodes via network links, each of...
US-7,251,175 Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power...
The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate...
US-7,251,159 Data encoding approach for implementing robust non-volatile memories
Data encoding system and method for implementing robust non-volatile memories. A data bit is stored using two memory cells. The data bit is represented by...
US-7,250,987 Method and system for an integrated VSB/QAM/NTSC/OOB plug-and-play DTV receiver
Certain embodiments of the invention may be found in a method and system for a vestigial side band (VSB), quadrature amplitude modulation (QAM), NTSC,...
US-7,250,980 Automatic detection of sync polarity in video timing and generation of blanking period indicator from sync...
The present invention relates to a system and method for generating a blanking period indicator signal from sync information in video timing. The invention...
US-7,250,887 System and method for spur cancellation
A system for spur cancellation comprises an input, an output, a memory, and a summer. A value corresponding to an energy level of a spur is stored in the memory....
US-7,250,802 Clock generator having a 50% duty-cycle
A method and apparatus for generating a fifty percent duty cycle clock from a reference clock. The method and apparatus includes an edge generator, a...
US-7,249,351 System and method for preparing software for execution in a dynamically configurable hardware environment
A system and method for creating run time executables in a configurable processing element array is disclosed. This system and method includes the step of...
US-7,248,858 Visitor gateway in a wireless network
A system and method for restricting access to a wireless network is disclosed herein. One or more access points are generally associated with the wireless...
US-7,248,844 Radio frequency integrated circuit electo-static discharge circuit
The radio frequency integrated circuit (RFIC) electrostatic discharge (ESD) circuit includes an integrated circuit pin and a radio frequency (RF) ESD circuit....
US-7,248,629 Efficient FIR filter for high-speed communication
A method for reducing a propagation delay of a digital filter. The digital filter has an input path and an output path and includes a set of delay elements and a...
US-7,248,101 Biasing scheme for low supply headroom applications
Methods and apparatus for improving the current matching within current mirror circuits in applications such as low voltage integrated circuits. Embodiments of...
US-7,248,081 Slicer with large input common mode range
A slicer with large input common mode range is provided. The slicer includes an input stage coupled to receive an input signal, a current source for providing...
US-7,246,341 Byte slice based DDR timing closure
Presented herein is a system and method for byte slice based DDR timing closure. In one embodiment, there is presented a method for synthesizing/laying out a...
US-7,246,245 System on a chip for network storage devices
In one embodiment, an apparatus includes a first integrated processor, a second integrated processor, and a security processor. The first integrated processor...
US-7,245,887 High speed CMOS transmit-receive antenna switch
A high-speed CMOS transmit/receive antenna switch includes a first transistor, a second transistor and a parasitic compensation network. The first transistor is...
US-7,245,638 Methods and systems for DSP-based receivers
Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and,...
US-7,245,621 Filtering and forwarding frames at an optical network node
An optical line terminal (OLT) monitors and controls communications with a plurality of optical nodes (ONs), such as optical network units (ONUs) and/or optical...
US-7,245,620 Method and apparatus for filtering packet data in a network device
A process of filtering packet data in a network device is disclosed. At least one mask is applied to a portion of an incoming packet and a field is extracted...
US-7,245,502 Small form factor USB bluetooth dongle
A small form factor USB Bluetooth dongle includes a printed circuit board (PCB), a USB contact area, and a radio frequency (RF) transceiver die. The PCB includes...
US-7,245,500 Ball grid array package with stepped stiffener layer
Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted on a first surface of a stiffener. A first...
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