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Fragment storage for data alignment and merger
A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a packet data transfer circuit...
Method and apparatus for efficient derivation of modulo arithmetic for
A method and apparatus for efficiently deriving modulo arithmetic solutions for frequency selection in transceivers. A frequency for communication between a...
Channel reciprocity matrix determination in a wireless MIMO communication
Operating a wireless MIMO system to determine forward and reverse channel reciprocity matrices relating a first wireless MIMO device and a second wireless MIMO...
Method and system for cellular network services and an intelligent
integrated broadcast television downlink...
In an RF communication system, aspects for cellular network and intelligent integrated broadcast television downlink with intelligent service control with...
Methods of recording voice signals in a mobile set
The present invention relates to a mobile set integrating a memory efficient data storage system for the real time recording of voice conversations, data...
Timing based LNA gain adjustment in an RF receiver to compensate for
A Radio Frequency (RF) receiver includes a low noise amplifier (LNA) and a mixer coupled to the output of the LNA. The gain of the LNA is adjusted to maximize...
Carrier based backwards compatible data networking transmitter, receiver,
and signal format
New version packet data devices support a backwards-compatible signal format. New version devices operate within a first frequency band while old version devices...
Parallel concatenated code with soft-in soft-out interactive turbo decoder
A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may...
Continuous-time delta-sigma ADC for a radio receiver employing 200 kHz IF
A Continuous-Time Delta-Sigma Analog-to-Digital Converter (CT.DELTA..SIGMA.ADC) for a radio frequency (RF) receiver employing a 200 kHz IF realizes an optimal...
Interpolating programmable gain attenuator
A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A...
Phase frequency detector with programmable delay
Methods and systems for locking a phase locked loop (PLL) are disclosed herein. A first impulse signal may be generated utilizing an input reference signal. A...
Method for assembling a ball grid array package with multiple interposers
Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted to a first surface of a first stiffener. A...
Programmable inter-virtual channel and intra-virtual channel instructions
issuing rules for an I/O bus of a...
A method and apparatus for programming instruction issuing rules for instructions residing among various virtual channels, as well as the same virtual channel of...
Wireless local area network supporting multiple slot times
A Wireless Local Area Network (WLAN) supports multiple slot times. A Basic Service Set (BSS)/Independent Basic Service Set (IBSS) of the WLAN services a...
Methods for performing channel diagnostics
A method is used to determine information about a communication channel using an adaptive filter coupled to the channel. The adaptive filter includes adaptive...
Pre-emphasis of TMDS signalling in video applications
The present invention relates to a system and method for improving the waveform at a receiver. More specifically, the present invention relates to a system...
8 PSK rotationally invariant turbo trellis coded modulation without
8 PSK (Phase Shift Keying) rotationally invariant turbo trellis coded modulation without parallel transitions. A novel approach of coding 8 PSK symbols such that...
Pipelining of multiplexer loops in a digital circuit
An n-level look-ahead network converts input values to intermediate values that are provided to a plurality of multiplexers arranged to form a pipelined...
Multiple virtual channels for use in network devices
A method for establishing a virtual channel between network devices is disclosed. In the case of a local network device establishing a virtual channel with a...
Digital IF demodulator with carrier recovery
A digital IF demodulator receives and demodulates an analog IF input signal to produce a digital audio signal and a digital video signal. The digital IF...
Method and system for providing edge antialiasing
A system and method for generating a graphical image on a display is disclosed. The graphical image is generated from data describing at least one object. The...
Apparatus and method for phase lock loop gain control
A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel...
Parallel decoding of a BCH encoded signal
A method or apparatus for error identification of a BCH encoded signal includes processing that begins by receiving a BCH encoded signal in a binary polynomial...
Power reduction for unintentional activation of a wireless input device
using a flip-flop to detect event...
An improved method and apparatus for reducing power consumption of a wireless input device when the wireless input device is unintentionally activated, and...
Pitch extraction methods and systems for speech coding using interpolation
A method of searching for an interpolated peak of a Normalized Correlation Square (NCS) signal derived from an audio signal, comprises: producing quadratically...
Downloading map segment(s) to a cell phone based upon its GPS coordinates
A wireless terminal displays its location and navigation information (map segment) on its display. The wireless terminal accesses a Global Positioning System...
Chip blanking and processing in SCDMA to mitigate impulse and burst noise
Systems and methods are disclosed for detecting temporary high level impairments, such as noise or interference, for example, in a communications channel, and...
Limited automatic repeat request protocol for frame-based communications
In a frame-switched network, a sender sends frames to a receiver over a possibly unreliable channel. Sent frames include frame identifiers that can be used for a...
Tracking multiple interface connections by mobile stations
A method and apparatus for communicating between devices is described. In one embodiment, the method comprises allowing a mobile station to have a first...
Using shadow Mcast/Bcast/Dlf counter and free pointer counter to balance
unicast and Mcast/Bcast/Dlf frame ratio
A network device for managing data flow can have at least one receiving port configured to receive data, a first counter configured to monitor at least one...
System and method for providing a low power receiver design
An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front...
System and method of transmission and reception of progressive content
with isolated fields for conversion to...
Systems and methods of coding progressive content with isolated fields for conversion to interlaced display are provided. Some systems and methods may find use...
Methods and systems for data manipulation
A method of and device for performing a data expansion operation on a plurality of input data objects to generate expanded output data objects is disclosed. The...
On-chip high Q inductor
A high-Q on-chip inductor includes a primary winding and an auxiliary winding. The primary winding includes a first node and a second node. The auxiliary winding...
Low phase noise crystal oscillator with supply noise filtering
A low phase noise crystal oscillator with supply noise filtering is provided and may comprise receiving an input voltage at a positive potential input of an...
Identification bit at a predetermined instruction location that indicates
whether the instruction is one or two...
An instruction set for a computer is described which includes instructions having a common predetermined bit length. That predetermined bit length can define a...
Peripheral component interconnect arbiter implementation with dynamic
A dynamic priority scheme is provided that uses information including the status of the target and data availability in deciding which PCI master should be...
Adjustable elasticity FIFO buffer have a number of storage cells equal to
a frequency offset times a number of...
A method of processing a data stream through a buffer is performed in accordance with a write clock and a read clock. The buffer has a plurality of sequentially...
Apparatus and method for converting a signal from a first analog format to
a second analog format
An apparatus for converting a signal from a first analog format to a second analog format. The apparatus has an input port, a first converter, filters, first...
RF transceiver with compact stacked mixer design for multiple frequency
A single chip radio transceiver includes circuitry that enables received wideband RF signals to be down-converted to baseband frequencies and baseband signals to...
Configuring a MIMO communication
A method for configuring a multiple input multiple output (MIMO) wireless communication begins by generating a first preamble for a first antenna of the MIMO...
Adaptive radio transceiver with filtering
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local...
Circuit output stage protection system
An output stage protection system for protecting NMOS devices in an integrated circuit (IC) output stage during normal operations and power up/power down. In an...
Method to improve high frequency divider bandwidth coverage
A divider for a local oscillator (LO) generator system of a phase locked loop (PLL) in a transceiver chip. The divider includes at least one divider unit. Each...
Method and apparatus for improving bus master performance
A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at...
Prioritization of real time / non-real time memory requests from bus
One or more methods and systems of prioritizing access of physical memory space to bus compliant devices in a computing device is presented. Prioritization is...
Method and apparatus for fractional-N synthesis
A method and apparatus for fractional-N synthesis includes processing that begins by generating a 1.sup.st feedback frequency from the output frequency based on...
System and method for DC offset compensation and bit synchronization
A system and method for compensating for DC offset and/or clock drift on a wireless-enabled device is described. One embodiment includes a radio module, an A/D...
Multiple time-base clock for processing multiple satellite signals
An integrated receiver with multiple, independently synchronized clock signals for multiple channel transport stream decoding and delivery substantially...
Determine coefficients of a decision feedback equalizer from a sparse
Determination of equalizer coefficients from a sparse channel estimate begins by determining location of significant taps based on the sparse channel estimate of...