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Patent # Description
US-7,230,983 Determine coefficients of a decision feedback equalizer from a sparse channel estimate
Determination of equalizer coefficients from a sparse channel estimate begins by determining location of significant taps based on the sparse channel estimate of...
US-7,230,982 Decision feedback equalizer for minimum and maximum phase channels
This invention describes an apparatus and method to improve the performance of a decision feedback equalizer (DFE) for time-varying multi-path channels. For...
US-7,230,872 Efficent column redundancy techniques
The present invention relates to a system and method adapted to increase memory cell and memory architecture design yield. The present invention includes memory...
US-7,230,652 System and method for providing picture-in-picture timebase management
Systems and methods that provide picture-in-picture timebase management are provided. In one example, a method may include the steps of sending a first video...
US-7,230,651 A/V decoder having a clocking scheme that is independent of input data streams
Devices and methods are disclosed for decoding data in a data stream. One embodiment relates to a method of decoding data using an A/V decoder. In this...
US-7,230,548 Method and apparatus for high performance key detection with key debounce
A system for detecting a key with key debounce including a circuit for detecting a key activation; a first counter coupled to the circuit and a clock for testing...
US-7,230,469 Multi-level/single ended input level shifter circuit
Methods are disclosed for translating or shifting a voltage level of a single ended input. More specifically, the present invention provides a method of...
US-7,228,392 Wireless data communications using FIFO for synchronization memory
A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there...
US-7,228,386 Programmably disabling one or more cache entries
A cache may be programmed to disable one or more entries from allocation for storing memory data (e.g. in response to a memory transaction which misses the...
US-7,227,871 Method and system for real-time change of slot duration
A supervisory communications device, such as a headend device within a cable communications network, monitors and controls communications with a plurality of...
US-7,227,870 Systems including packet interfaces, switches, and packet DMA circuits for splitting and merging packet streams
An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets...
US-7,227,862 Network switch having port blocking capability
A switch is configured to block packets from being transmitted through designated ports. The switch has port bitmap generator configured to obtain a port bitmap...
US-7,227,587 System and method for three dimensional comb filtering
A system and method for determining whether to process a signal using three-dimensional comb filtering. Various aspects of the present invention may comprise...
US-7,227,582 Graphics display system with video synchronization feature
A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video...
US-7,227,554 Method and system for providing accelerated video processing in a communication device
Providing accelerated video processing in a communication device may comprise receiving video data from a video source on a chip, determining a first format for...
US-7,227,411 Apparatus for a differential self-biasing CMOS amplifier
Aspects of the invention provide a self-biasing differential amplifier. The self-biasing differential amplifier may include a first input stage and a biasing...
US-7,227,256 Die-up ball grid array package with printed circuit board attachable heat spreader
An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate...
US-7,227,238 Integrated fuse with regions of different doping within the fuse neck
An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The...
US-7,224,726 System and method for terrestrial high-definition television reception
An adaptive receiver is disclosed for optimally receiving and processing signals. The receiver utilizes one or more memory blocks to store groups of incoming...
US-7,224,723 Handshaking communication system and method for multiple xDSL
A system and method for handshaking multiple xDSL technologies is provided. More particularly, the present invention provides a means for new xDSL technologies...
US-7,224,722 Direct conversion RF transceiver with automatic frequency control
A single chip radio transceiver includes circuitry that enables received wideband RF signals to be down-converted to baseband frequencies and baseband signals to...
US-7,224,692 System and method for fault tolerant TCP offload
Systems and methods that provide fault tolerant transmission control protocol (TCP) offloading are provided. In one example, a method that provides fault...
US-7,224,304 Method and apparatus for an image canceling digital-to-analog converter (DAC)
A method and apparatus for an image canceling digital-to-analog converter is disclosed. Up-sampling and noise shaping is used to produce a stream of digital...
US-7,224,234 Apparatus and method for phase lock loop gain control using unit current sources
A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel...
US-7,224,156 Voltage regulator for use in portable applications
A voltage regulator includes a first stage capable having a first current flowing through it. A second stage has a second current. A third stage is capable of...
US-7,222,202 Method for monitoring a set of semaphore registers using a limited-width test bus
Certain embodiments of the invention may be found in a method and system for monitoring a set of semaphore registers using a limited-width test bus. Each...
US-7,221,946 Automatic quality of service based resource allocation
A system and method for providing quality-of-service based network resource allocation and utilization in a dynamic network environment. For example, a wireless...
US-7,221,717 Bluetooth access code assisted initial DC estimation and frame synchronization
A system for calculating DC offset and achieving frame detection is described. In one embodiment, the present invention includes an electronic device with an...
US-7,221,714 Non-systematic and non-linear PC-TCM (Parallel Concatenate Trellis Coded Modulation)
Non-systematic and non-linear PC-TCM (Parallel Concatenate Trellis Coded Modulation). A non-systematic and non-linear PC-TCM code is presented that provides...
US-7,221,577 Bus twisting scheme for distributed coupling and low power
The present invention relates to a system and method for equalizing the capacitance between/among n lines of a bus running in parallel for a portion of their...
US-7,221,234 VCO with switchable varactor for low KVCO variation
A method and system for VCO with switchable varactor for low KVCO variation is provided. Aspects of a method for controlling a signal may comprise controlling an...
US-7,219,353 Finite state machine with a single process context for a RAID system
A finite state machine (FSM) for a redundant array of independent disk includes a single process context that maintains an entire finite state required for...
US-7,219,216 Method for identifying basic blocks with conditional delay slot instructions
A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot...
US-7,219,118 SIMD addition circuit
A system for adding multiple sets of numbers via a fixed-width adder includes an adder for receiving each of the sets of binary numbers at corresponding sets of...
US-7,218,911 Communication device with a self-calibrating sleep timer
The present invention provides for a system for operating a communication device (20) for reception of scheduled intermittent information messages (22) with a...
US-7,218,909 Integrated low noise amplifier
An integrated circuit (IC) low noise amplifier includes an on-chip balun and an on-chip differential amplifier. The on-chip balun is operably coupled to convert...
US-7,218,694 System and method for canceling interference in a communication system
A filter settings generation operation includes sampling a communication channel to produce a sampled signal. The sampled signal is spectrally characterized...
US-7,218,645 Method and apparatus optimizing a radio link
Optimizing a radio link is done by acquiring at least OSI layer one and two performance measurements, determining an optimum setting collection for at least OSI...
US-7,218,638 Switch operation scheduling mechanism with concurrent connection and queue scheduling
A system for servicing data transactions within a processing device using common data paths. The system is broadly comprised of: a plurality of source agents...
US-7,218,258 Method and system for mixed analog-digital automatic gain control
Aspects of the invention provide a method and system for a mixed analog-digital automatic gain control. The received analog signal is amplified by the analog...
US-7,218,253 Hardware efficient implementation of finite impulse response filters with limited range input signals
Disclosed herein is a method and system to reduce the area and power dissipation in digital filters or multipliers. Compared to radix-4 Booth coding the proposed...
US-7,218,170 Multi-pole current mirror filter
A current mirror with selectable filter poles provides a selected low pass filtering function to a DC bias signal generated by the current mirror. Coupled...
US-7,218,156 Supply tracking clock multiplier
A circuit for and method of operating a supply tracking clock multiplier is provided. An embodiment of the present invention may permit a less power consuming...
US-7,216,283 Iterative metric updating when decoding LDPC (low density parity check) coded signals and LDPC coded modulation...
Iterative metric updating when decoding LDPC (Low Density Parity Check) coded signals and LDPC coded modulation signals. A novel approach is presented for...
US-7,216,218 Microprocessor with high speed memory integrated in load/store unit to efficiently perform scatter and gather...
The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values...
US-7,215,934 Iterative multi-stage detection technique for a diversity receiver having multiple antenna elements
An iterative multistage detection system and method for orthogonally multiplexing K channels onto a signal processing chain using N orthogonal sequences of...
US-7,215,932 On-chip impedance matching power amplifier
An on-chip impedance matching includes a transistor and a tank circuit. The transistor is operably coupled to receive an input signal. The tank circuit is...
US-7,215,923 System and method for establishing a connection between wireless devices
A system and method according to the present invention allow two or more peer-to-peer wireless devices to automatically connect to each other with no knowledge...
US-7,215,727 Impulse noise detection from preamble symbols
A communication device constructed according to the present invention detects impulse noise in a preamble sequence. In detecting impulse noise in the preamble...
US-7,215,725 Enhanced channel parameter estimation in the presence of preamble erasures
A communication device processes a preamble in the presence of impulse noise. The communication device receives a preamble sequence that includes a plurality of...
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