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Patent # Description
US-7,203,164 Voice architecture for transmission over a shared, contention based medium
A control terminal such as a CMTS is initialized to receive packets of voice calls having parameters including a bit rate, a packetization interval, and a call...
US-7,202,757 Compact balun with rejection filter for 802.11a and 802.11b simultaneous operation
A balancing/unbalancing (balun) structure includes two input ports are coupled to a differential signal. An isolated port is connected to ground through a...
US-7,202,755 Semi-suspended coplanar waveguide on a printed circuit board
A printed circuit board includes two differential signal traces, a layer of core material, a layer of filler material, and a ground plane. The filler material is...
US-7,202,749 AC coupling technique for improved noise performance and simple biasing
A low noise amplifier (LNA), which utilizes an AC coupling technique that can internally bias diodes in such a way as to provide effective low noise...
US-7,202,740 Gain boosting for tuned differential LC circuits
A gain boost circuit and methodology are described for providing improved gain boosting with tuned amplifier circuits, such as differential low noise amplifier...
US-7,202,707 High frequency binary phase detector
A phase detector includes a first flip flop having a data input coupled to a first clock signal at a first frequency and a clock input coupled to a second clock...
US-7,202,559 Method of assembling a ball grid array package with patterned stiffener layer
Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. An IC die is mounted in a centrally located cavity of a...
US-7,200,724 Two dimensional data access in a processor
A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first...
US-7,200,379 Low-power mode clock management for wireless communication devices
A power management scheme for a wireless communications device substantially implemented on a single CMOS integrated circuit is described. The present invention...
US-7,200,370 Power amplifier having enhanced swing cascode architecture
A Radio Frequency (RF) power amplifier includes a transconductance stage, an AC coupling element, and a cascode stage. The transconductance stage is adapted to...
US-7,199,737 Disconnecting a time discrete circuit from a track-and-hold circuit in track mode
A system and method for an improved analog front-end system is disclosed. By coupling a switch to the output of a track-and-hold circuit and to the input of a...
US-7,199,670 Use of a thick oxide device as a cascode for a thin oxide transconductance device in MOSFET technology and its...
A power amplifier power amplifier includes a transconductance stage and a cascode stage. The transconductance stage that is operable to receive an input voltage...
US-7,199,664 Integrated switchless programmable attenuator and low noise amplifier
An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front...
US-7,199,659 Non-match power amplifier and method for increased output 1 dB compression point
The invention enables an increase in linear power output ranges in a power amplifier by using an unmatched power amplifier driver in place of a matched power...
US-7,199,612 Method and circuit for reducing HCI stress
Systems and methods are disclosed for reducing or eliminating hot carrier injection stress in circuits. In one embodiment, the present invention relates to an...
US-7,197,690 Bandwidth efficient coded modulation scheme based on MLC (multi-level code) signals having multiple maps
Bandwidth efficient coded modulation scheme based on MLC (Multi-Level Code) signals having multiple maps. The use of multiple maps is adapted to various types of...
US-7,197,600 Transferring data along with code for program overlays
The present invention provides a method for use with program overlays, wherein code segments, along with data segments pertaining to the code segments, are...
US-7,197,548 Method and apparatus for verifying connectivity among nodes in a communications network
For each node, elapsed periodic time intervals are provided and counted since the transmission of a link integrity indication frame, a frame which can be...
US-7,197,421 Method and system for a temperature sensor for transmitter output power compensation
In an RF communication system, aspects of a method for a temperature sensor for transmitter output power compensation may comprise generating an output voltage,...
US-7,197,276 Downstream adaptive modulation in broadband communications systems
A downstream adaptive modulation system and method. The downstream adaptive modulation system comprises a wireless access termination system and one or more...
US-7,197,096 Compensation of reference frequency drift in system requiring critical upstream timing
Systems and methods are disclosed for to compensating reference frequency drift in a communications system having a plurality of modems and a headend, where the...
US-7,197,069 Multi-pair gigabit ethernet transceiver having adaptive disabling of circuit elements
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver...
US-7,197,068 Non-iterative time-domain equalizer
A method for forming a non-iterative time-domain equalizer (TEQ) and apparatus corresponding thereto. A channel response H(z) is followed by a TEQ response A(z)...
US-7,197,044 Method for managing congestion in a network switch
A method for managing congestion in a stack of network switches includes the steps of receiving an incoming packet on a first port of a network switch for...
US-7,196,582 Method and system for low noise amplifier (LNA) and power amplifier (PA) gain control
Methods and systems for processing signals are disclosed herein. In one aspect of the invention a circuit for processing signals may comprise a triple well (TW)...
US-7,196,559 Multi-modulus divider for high speed applications
A multi-modulus divider for high speed applications is provided and may comprise a multistage divider generating a divided signal from an output portion of a...
US-7,196,415 Low voltage drop and high thermal performance ball grid array package
An apparatus and method for a low voltage drop and thermally enhanced integrated circuit (IC) package are described. A substantially planar substrate having a...
US-7,194,627 Method and system for data encryption and decryption
An aspect of the of the invention may include the transfer of a block of data from a first memory location to a second memory location in a DRAM. During the...
US-7,194,029 Multi-pair gigabit ethernet transceiver having adaptive disabling or circuit elements
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver...
US-7,194,028 Multi-Pair Gigabit Ethernet Transceiver having decision feedback equalizer
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver...
US-7,194,008 Method and apparatus for parsing data streams
A system includes an interface, a synchronization module, a pre-filtering module and a data alignment module. The interface is configured to connect a first...
US-7,193,656 Line address computer for providing coefficients to a chroma filter
Presented herein is a line address computer for providing chroma coefficients to a chroma filter. At each horizontal synchronization pulse, the line address...
US-7,193,464 Differential amplifier with large input common mode signal range
A design for a differential amplifier with a large input common mode signal range. The differential amplifier comprises two differential pairs, each having two...
US-7,191,341 Methods and apparatus for ordering data in a cryptography accelerator
Methods and apparatus are provided for sequencing data in a cryptography accelerator with multiple cryptographic processing cores. Cryptographic processing cores...
US-7,191,317 System and method for selectively controlling operations in lanes
A method and system for conditionally carrying out an operation defined in a computer instruction wherein a computer instruction is implemented on so-called...
US-7,191,279 Schmoo runtime reduction and dynamic calibration based on a DLL lock value
Methods of setting numerically controlled delay lines using step sizes based on a delay locked loop lock value are presented herein. In one embodiment, a method...
US-7,191,203 Method and system for high-speed multiplication
A system, method, and computer product for high-speed multiplication of binary numbers. A multiplier X is first encoded, and the encoded multiplier is then used...
US-7,190,974 Shared antenna control
A scheme for sharing antenna control pins in a wireless communications device implemented on a single CMOS integrated circuit is described. By providing a...
US-7,190,906 Linear full-rate phase detector and clock and data recovery circuit
Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate...
US-7,190,775 High quality audio conferencing with adaptive beamforming
Systems and methods that enable high quality audio teleconferencing are disclosed. In one embodiment of the present invention, a signal processor receives...
US-7,190,727 Categorization of impairments affecting a communication channel
An impairment compensation sequence for use in a communications system susceptible to one or more potential impairments each periodic in an integer number of...
US-7,190,718 Method and apparatus for determining a receiver sampling phase for use in diagnosing a channel
An apparatus for processing a received signal includes an analog-to-digital converter (ADC) configured to produce a sampled signal from a received signal using a...
US-7,190,710 Successive interference canceling for CMDA
Successive interference canceling for CMDA. ICI may result from a signal's multipath effects, or by filtering/suppression of some of the component energy of the...
US-7,190,704 Cable modem system with sample and packet synchronization
A method for communicating information is disclosed wherein a time slot is allocated in a time division multiple access system for a transmission from a...
US-7,190,298 Resistor ladder interpolation for subranging ADC
An analog to digital converter includes a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a...
US-7,190,296 Low power, high SNR, high order delta sigma modulator stage having integrators with pipelined cross coupled...
In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator...
US-7,190,219 Extended range variable-gain amplifier
An extended range variable gain amplifier is described. The variable gain capability is achieved by replacing differential pair amplifiers having an input signal...
US-7,188,301 Parallel concatenated turbo code modulation encoder
Parallel concatenated turbo trellis encoder structure. A dual path turbo trellis coded modulation encoder employs two interleavers and two constituent encoders...
US-7,188,192 Controlling multiple context processing elements based on transmitted message containing configuration data,...
A method and apparatus for providing local control of processing elements in a network of multiple context processing elements (MCPEs). A MCPE stores...
US-7,187,916 Method and system for measuring receiver mixer IQ mismatch
Aspects for measuring receiver mixer IQ mismatch in a transceiver are described. The measuring includes providing a training signal for a receiver mixer, the...
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