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Patent # Description
US-7,154,974 Data recovery system and applications thereof in radio receivers
A method and apparatus for data recovery includes processing that begins by receiving an encoded signal at a transmit symbol rate. Such an encoded signal...
US-7,154,877 System and method for best effort scheduling
A system and method for increasing bandwidth usage between an access point and a wireless device are described. One embodiment can include an access point, a...
US-7,154,810 Synchronous controlled, self-timed local SRAM block
The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local...
US-7,154,407 Apparatus and method for displaying system state information
A programmable LED display system is disclosed. The system includes a programmable controller; a driver operative to generate a control signal in response to a...
US-7,154,346 Apparatus and method to provide a local oscillator signal
An apparatus provides a local oscillator signal based on a selected channel of an RF input signal. For example, the apparatus can set a frequency of the local...
US-7,152,176 Dynamic resynchronization of clocked interfaces
One or more methods and systems of resynchronizing or dynamically retuning a clock signal over a high speed clocked data interface are presented. In one...
US-7,152,118 System, method and computer program product for caching domain name system information on a network gateway
A system, method and computer program product is provided for caching domain name system (DNS) information on a network gateway. In particular, a network gateway...
US-7,151,894 Bit error rate based system and method for optimizing communication system performance
A system (50) includes a communication path (170) and transmits data on a network (103, 106). A transmitter (101) transmits data on the network and a receiver...
US-7,151,796 High performance equalizer with enhanced DFE having reduced complexity
An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP)...
US-7,151,745 Scalable synchronous packet transmit scheduler
A baseband controller system creates and maintains a schedule of synchronized events and reviews the schedule as a part of determining whether to initiate a...
US-7,151,660 High density maze capacitor
A capacitor including a first and second component capacitor structure disposed on a substrate. A component capacitor structure includes a first arm, a second...
US-7,151,416 Apparatus and method to generate a 50% duty cycle clock in a single-ended crystal oscillator
A clock generator includes an active oscillator portion that generates an oscillating signal having a frequency determined by a resonator, such as a crystal or...
US-7,149,954 Method and system for programmable field statistic for picture cyclic redundancy check (CRC)
Provided is a system and method for performing CRC analysis in a video test bench. An exemplary system includes a memory configured for storing a required number...
US-7,149,953 Efficient LDPC code decoding with new minus operator in a finite precision radix system
Efficient LDPC code decoding with new minus operator in a finite precision radix system. A new mathematical operator is introduced and applied to the decoding of...
US-7,149,492 Method to improve CMFB phase margin of variable-output-bandwidth mixer
An improved method and apparatus for using common mode feedback to maintain a predetermined DC level for an intermediate frequency output signal. A common mode...
US-7,149,488 Direct tuning of radio receiver integrated circuit
A method for direct tuning of a radio receiver begins by providing a plurality of frequency-dependent control input signals to an input of the radio receiver....
US-7,149,474 Wireless cable replacement system
A wireless cable replacement system. A personal area network, comprising a device having a first wireless transceiver, and an adapter having a second wireless...
US-7,149,305 Combined sidetone and hybrid balance
A combined sidetone and hybrid balance apparatus and method of operating same are disclosed. An embodiment of the present invention may provide both a hybrid...
US-7,149,248 Command packet system and method supporting improved trick mode performance in video decoding systems
A system, method, and apparatus for reducing the video decoder processing requirements are presented herein. During a rewind operation, a reference picture for a...
US-7,149,196 Location tracking in a wireless communication system using power levels of packets received by repeaters
A location tracking apparatus and method are disclosed. In one embodiment, the method comprises receiving information from each repeater indicating which packets...
US-7,148,845 Antenna array including virtual antenna elements
A method and associated system for effectively increasing the number of antenna elements within a multi-element antenna system through computation of a response...
US-7,148,825 Data interface including gray coding
A data interface includes a network interface processor, a transmitter, and a receiver. The network interface processor is operably coupled to transceive...
US-7,148,750 Gigabit ethernet transceiver with analog front end
Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain...
US-7,146,580 Interchangeable integrated circuit building blocks
Interchangeable integrated circuit building blocks include functionally equivalent integrated circuit building blocks, having similar footprints, and having one...
US-7,146,391 Method and system for implementing SLICE instructions
Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed...
US-7,145,888 Explicit congestion notification for DOCSIS based broadband communication systems
Satellite communications are carried out using the Data Over Cable Interface Specification (DOCSIS). Satellite modems are notified of upstream channel congestion...
US-7,145,869 Method for avoiding out-of-ordering of frames in a network switch
A method for avoiding out-of-ordering of frames in a network, wherein the method includes the steps of providing at least one first type of queue in a network...
US-7,145,488 Method and system for converting digital samples to an analog signal
Provided is a system and method for converting digital data audio data audio data that has a predetermined input sample rate, into an analog data signal. A...
US-7,145,390 Differential power amplifier and method in class AB mode
The invention enables an increase in linearity of a power amplifier while reducing current consumption by supplying a bias current to the power amplifier in a...
US-7,145,315 Over-current detection circuit in a switch regulator
A switch regulator includes an inductor, a reference transistor, a first switching transistor, and a second switching transistor. The first switching transistor...
US-7,145,188 Apparatus and method of image processing to avoid image saturation
An imaging device includes a plurality of photo-diodes that operate as optical pixels arranged in a plurality of columns on a single CMOS substrate. The outputs...
US-7,143,294 Apparatus and method for secure field upgradability with unpredictable ciphertext
An apparatus and method for enabling functionality of a component, wherein the apparatus includes a random number generating module for generating a random...
US-7,143,265 Computer program product memory access system
A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two...
US-7,143,073 Method of generating a test suite
The invention relates to generating a test suite of instructions for testing the operation of a processor. A fuzzy finite state machine with a plurality of...
US-7,143,032 Method and system for an overlap-add technique for predictive decoding based on extrapolation of speech and...
A method and system are provided for removing discontinuities associated with synthesizing a corrupted frame output from a decoder including one or more...
US-7,142,671 Methods and apparatus for implementing a cryptography engine
Methods and apparatus are provided for implementing a cryptography engine for cryptography processing. A variety of techniques are described. A cryptography...
US-7,142,618 Receiver having decisional feedback equalizer with remodulation and related methods
A receiver includes a filter for filtering a received signal to produce a filtered signal. A converter converts the filtered signal to a baseband signal that is...
US-7,142,553 Off-line broadband network interface
A network interface is presented that receives packet data from a shared medium and accomplishes the signal processing required to convert the data packet to...
US-7,142,539 TCP receiver acceleration
A transport protocol receiver for receiving a packet from a network, the packet having a header, payload, and connection context. The receiver includes an...
US-7,142,535 Hierarchical data collection network supporting packetized voice communications among wireless terminals and...
A packet-based, hierarchical communication system, arranged in a spanning tree configuration, is described in which wired and wireless communication networks...
US-7,142,139 Powering down of DAC and ADC for receive/transmit modes of operation in a wireless device
A digital-to-analog converter (DAC) disposed in a data transmission path to convert data from a digital format to an analog format to be transmitted is powered...
US-7,142,057 System to accelerate settling of an amplifier
A system and method are used to accelerate settling or steady state of an amplifier in an amplifier system. This is used to ensure the amplifier reaches...
US-7,142,056 Operational amplifier with increased common mode input range
An operational amplifier includes a first stage with a first differential transistor pair inputting a differential input signal at their gates, a first tail...
US-7,142,039 Regulated charge pump with digital resistance control
A charge pump includes a resistor divider connected between an output voltage node and ground and a comparator inputting a reference voltage at one input, and a...
US-7,142,036 Amplifier compensation techniques for switched capacitor circuits
A system and method are used to maintain a variance in feedback factors of an amplifier between the first and second phases either below a threshold value or...
US-7,142,013 One-level zero-current-state exclusive or (XOR) gate
Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured...
US-7,141,986 Using time domain reflectometry to detect mismatched cable/connector interface
A system for detecting connector compatibility with a time domain reflectometry (TDR) circuit on a peripheral device. A cable connects the peripheral device and...
US-7,139,964 Variable modulation with LDPC (low density parity check) coding
Variable modulation within combined LDPC (Low Density Parity Check) coding and modulation coding systems. A novel approach is presented for variable modulation...
US-7,139,902 Implementation of an efficient instruction fetch pipeline utilizing a trace cache
A method and apparatus are disclosed for enhancing the pipeline instruction transfer and execution performance of a computer architecture by reducing instruction...
US-7,139,789 Adder increment circuit
In association with a circuit for adding binary numbers, it is often useful to increment the sum by a value of 1, for example on a conditional basis. Each of the...
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