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Patent # Description
US-7,139,540 Adaptive radio transceiver with calibration
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local...
US-7,139,339 Iterative data-aided carrier frequency offset estimation for code division multiple access systems
Iterative data-aided carrier CFO estimation for CDMA systems. Any communication receiver may be adapted to perform the iterative data-aided carrier CFO...
US-7,139,337 Efficient partial response equalization
A reduced state maximum likelihood sequence estimator allows the use of improved equalization techniques that provides greatly improved performance for channels...
US-7,139,335 Optimal decision metric approximation in bit-soft decisions
Optimal decision metric approximation in bit-soft decisions. The present invention provides for calculation of the decision metrics/branch metrics for...
US-7,139,332 Quadrature receiver sampling architecture
Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I...
US-7,139,331 Characterizing channel response in a single upstream burst using redundant information from training tones
Characterizing channel response in a single upstream burst using redundant information from training tones (TTs). The invention is operable to utilize inserted...
US-7,139,283 Robust techniques for optimal upstream communication between cable modem subscribers and a headend
A number of features for enhancing the performance of a cable transmission system in which data is transmitted between a cable modem termination system at a...
US-7,139,269 Cascading of gigabit switches
A method of handling data packets in a series of network switches includes receiving an incoming data packet at a data port of a first switch of the series of...
US-7,138,876 Use of a thick oxide device as a cascode for a thin oxide transconductance device in MOSFET technology and its...
A power amplifier power amplifier includes a transconductance stage and a cascode stage. The transconductance stage that is operable to receive an input voltage...
US-7,138,847 Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations
A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the...
US-7,138,836 Hot carrier injection suppression circuit
A method of preventing Hot Carrier Injection in input/output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so...
US-7,138,834 Symmetric differential logic circuits
Embodiments of the present invention perform logical operations utilizing a symmetric logic circuit comprising two logic units. In a symmetric logic circuit, the...
US-7,137,059 Single stage implementation of min*, max*, min and /or max to perform state metric calculation in SISO decoder
Single stage implementation of min*, max*, min and/or max to perform state metric calculation in soft-in soft-out (SISO) decoder. This allows for calculation of...
US-7,137,054 System and apparatus for scanning integrated circuits with numerically controlled delay lines
A system and method for scan testing an NCDL and latches controlled by the NCDL is presented. The NCDL is controlled by control logic, a switch is used to...
US-7,137,046 High speed comparator for 10G SERDES
An error counter including receive logic to compare transmitted bits with received bits and output a vector with a logic 1 for every bit that does not match and...
US-7,136,985 Method and system for fast data access using a memory array
First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits....
US-7,136,630 Methods of recording voice signals in a mobile set
The present invention relates to a mobile set integrating a memory efficient data storage system for the real time recording of voice conversations, data...
US-7,136,622 Adaptive radio transceiver with noise suppression
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local...
US-7,136,435 Modified branch metrics for processing soft decisions to account for phase noise impact on cluster variance
Modified branch metrics for processing bit-soft decisions to account for phase noise impact on cluster variance (CV). The present invention is able to partition...
US-7,136,432 Robust burst detection and acquisition system and method
A method of parameter estimation in a shared channel communications system includes the steps of receiving a preamble including a first sequence corresponding to...
US-7,136,431 DC offset correcting in a direct conversion or very low IF receiver
A direct conversion or VLIF receiver corrects DC offset by, prior to receiving a burst of data, the receiver determines a coarse DC offset with the antenna of...
US-7,136,381 Memory management unit architecture for switch fabric
A memory management unit (MMU) for a network switch fabric for forwarding data is disclosed. The MMU has an ingress port interface receiving portions of a data...
US-7,136,303 System and method using a one-time programmable memory cell
A one-time programmable device includes a controller, a protection system, a static storage element and a latch, which can be referred to as a latch-based...
US-7,135,942 Interpolating programmable gain attenuator
A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A...
US-7,135,930 Switched supply for operational amplifier
There is provided a circuit and method for providing a supply voltage to an operational amplifier. A switch has a plurality of inputs connected to a respective...
US-7,135,928 Method for transconductance linearization for DC-coupled applications
A Class AB voltage-to-current converter includes a plurality of DC coupled transconductance stages that produce a linearized output and a biasing circuit. The...
US-7,135,926 Adaptable voltage control for a variable gain amplifier
A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain...
US-7,135,905 High speed clock and data recovery system
A clock and data recovery system for detecting and resolving meta-stability conditions is provided. The clock and data recovery system includes a phase detector...
US-7,135,889 Universal single-ended parallel bus
A high speed data communication system uses a single-ended bus architecture with a reference signal extracted from a differential periodic signal that is...
US-7,135,730 Bias-independent capacitor based on superposition of nonlinear capacitors for analog/RF circuit applications
A first MOS-on-NWELL device is formed on a substrate and has its pickup terminals optionally connected together. A second MOS-on-NWELL device is formed on the...
US-7,134,038 Communication clocking conversion techniques
A plurality of groups of first flip-flops (group 40 of flip-flops A1 An-1 for each of channels CIA CIC) store input data clocked in response to first clock...
US-7,134,014 Methods and apparatus for accelerating secure session processing
Methods and apparatus are provided for an entity such as a CPU to efficiently call a cryptography accelerator to perform cryptographic operations. A function...
US-7,134,010 Network interface with double data rate and delay locked loop
A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The...
US-7,133,655 Amplifiers and amplifying methods for use in telecommunications devices
A signal strength indicator circuit that includes a first amplifier configured to receive a first input signal from a first mixer and a second input signal from...
US-7,133,645 Transceiver with optimal antenna direction indicators
A wireless access point includes, in one embodiment, circuitry with a radio transceiver that determines substantially optimal antenna orientation for one or more...
US-7,133,449 Apparatus and method for conserving memory in a fine granularity scalability coding system
Decoding time stamps (DTSs) and presentation time stamps (PTSs) are used in fine granularity scalability (FGS) coding during MPEG-4 video coding. An input video...
US-7,133,443 Multi-tone transmission
A Multi-tone transmission system processes input data through a plurality of intermediate processing stages 12,14,16 and corresponding stages of intermediate...
US-7,133,046 System, method, and apparatus for display manager
A system, method, and apparatus for decoding and displaying images utilizing two processors and two memory units. The decode process receives images which are...
US-7,132,970 Delay equalized Z/2Z ladder for digital to analog conversion
A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors...
US-7,132,968 Hardware-efficient implementation of dynamic element matching in sigma-delta DAC's
A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x.sub.0 and x.sub.1 of the input...
US-7,132,888 Large gain range, high linearity, low noise MOS VGA
An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides...
US-7,132,880 High bandwidth, high PSRR, low dropout voltage regulator
A voltage regulator may include one or more features for generating high PSRR. For example, source follower devices may be included in the voltage regulator for...
US-7,132,866 Method and apparatus for glitch-free control of a delay-locked loop in a network device
A method of controlling a delay-locked loop (DLL) module is disclosed. The method includes the steps of receiving a clock signal, comparing the received clock...
US-7,132,744 Enhanced die-up ball grid array packages and method for making the same
An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate...
US-7,132,727 Layout technique for C3MOS inductive broadbanding
An improved cell layout for a C3MOS circuit with inductive broadbanding positions the inductor at a distance from the active region to improve isolation and...
US-7,131,045 Systems and methods for scan test access using bond pad test access circuits
The present invention is directed to circuits and methods to efficiently conduct scan testing of integrated circuits in which first level packaging is varied to...
US-7,131,020 Distributed copies of configuration information using token ring
A system for synchronizing configuration information in a plurality of data processing devices using a common system interconnect bus. The present invention...
US-7,131,001 Apparatus and method for secure filed upgradability with hard wired public key
An apparatus and for enabling functionality of a component, wherein the apparatus includes an identification module having an identification number stored...
US-7,130,985 Parallel processor executing an instruction specifying any location first operand register and group...
Described herein is a data processor that comprises a register memory and a processor unit. The processor unit simultaneously executes a single instruction on a...
US-7,130,953 Bus architecture techniques employing busses with different complexities
An integrated circuit system (70) includes a processor (130) and a system bus (12) with a first complexity coupled to the processor. Apparatus for enabling...
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