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Patent # Description
US-7,130,670 Wireless network card with antenna selection option
A wireless network card includes an adaptable antenna connection structure that includes connections for one or more internal antennas and for one or more Radio...
US-7,130,607 Adjusting a programmable mixer
A method for adjusting a programmable mixer of a local oscillation module to reduce local oscillation leakage begins by determining at least one of: DC offset of...
US-7,130,601 Determination of received signal strength in a direct conversion receiver
Determination of a received signal strength indication in a direct conversion receiver begins by determining, at a given time, a 1.sup.st value to be the larger...
US-7,130,579 Adaptive radio transceiver with a wide tuning range VCO
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local...
US-7,130,395 Method and system for reducing cross-talk and avoiding bridged taps
The present invention establishes a communications link between a central office (CO) modem and a customer premise equipment (CPE) modem. The CO modem then...
US-7,130,314 Efficiently transmitting RTP protocol in a network that guarantees in order delivery of packets
A method and computer program product for providing RTP suppression across a DOCSIS network. An index number and a set of rules are sent to a receiver. The index...
US-7,129,871 Digital-to-analog converter with programmable current control
A wide gain range current digital-to-analog converter (DAC) is presented that includes a unit current cell having a current source module biased by a current...
US-7,129,865 High speed, low power comparator
A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in...
US-7,129,803 Tuned transformer balun circuit and applications thereof
A tuned transformer balun circuit includes a transformer balun, a first tuning capacitor, a second tuning capacitor, and a third tuning capacitor. A first plate...
US-7,129,792 Apparatus and method for phase lock loop gain control using unit current sources
A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel...
US-7,129,787 Systems and methods for ramping power amplifier output power
A power amplifier circuit including a first transistor, a second transistor, and a power control circuit. The first transistor includes a first input and a first...
US-7,129,785 Methods and systems for biasing a power amplifier
An amplifier circuit including a first transistor and a biasing circuit. The biasing circuit includes a process compensation circuit. The biasing circuit being...
US-7,129,784 Multilevel power amplifier architecture using multi-tap transformer
A multi-level power amplifier architecture using a multi-tap transformer implemented on a single CMOS integrated circuit wireless communications device is...
US-7,129,755 High-fanin static multiplexer
An improved high-fanin multiplexer that is highly-scalable, fast and area-efficient. In one embodiment of the present invention, multiple logic "legs" are...
US-7,129,697 Dynamic register with IDDQ testing capability
The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating...
US-7,129,589 Use of an internal on-chip inductor for electrostatic discharge protection of circuits which use bond wire...
A circuit includes a plurality of circuit components formed on a semi conductive substrate die and a bond wire. The plurality of circuit components include at...
US-7,129,574 Multi-power ring chip scale package for system level integration
A scalable multi-power integrated circuit package for integrated circuits having spaced apart first, second and third pluralities of respective spaced apart chip...
US-7,127,648 System and method for performing on-chip self-testing
A method for determining whether a physical layer device under test is defective may include establishing a closed communication path between a verified physical...
US-7,127,624 Energy detect with auto pair select
Energy detect with auto pair select. The present invention is operable without `a priori` knowledge of the pairs' connectivity. In addition, the present...
US-7,127,593 Conditional execution with multiple destination stores
A method for conditionally performing a SIMD operation causing a predetermined number of result objects to be held in a combination of different ones of a...
US-7,127,222 Automatic gain control adjustment of a radio receiver
A method for adjusting automatic gain control of a radio receiver begins by determining power level of a radio frequency (RF) signal received by the radio...
US-7,127,167 System for spectrum allocation in ethernet-based fiber optic TDMA networks
A system for management of bandwidth, cost control, and operational efficiency in a fiber optic, ethernet-based, TDMA communications system. The invention...
US-7,127,007 Method, apparatus and system for high-speed transmission on fiber optic channel
Multi-carrier modulation fiber optic systems constructed using a series of electrical carriers, modulating the data on the electrical carriers and combining the...
US-7,126,947 Switch having external address resolution interface
A network switch that has a plurality of input ports that receive data packets. An external interface is connected to the plurality of input ports. The external...
US-7,126,428 Radio frequency variable gain amplifier with linearity insensitive to gain
A multi-stage, variable gain amplifier whose linearity is relatively insensitive to variations in gain control is disclosed. The amplifier includes a primary...
US-7,126,377 Linear buffer
A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output...
US-7,126,319 Low leakage CMOS power mux
A power supply multiplexing circuit including a first supply voltage input. A first pair of cascoded PMOS transistors are in series with the first supply voltage...
US-7,124,330 Physical layer loop back method and apparatus
The network device includes a transceiver, a pattern generation unit and a pattern recognition unit. The transceiver connects to a communications medium. The...
US-7,124,296 Security chip architecture and implementations for cryptography acceleration
An architecture and a method for cryptography acceleration is disclosed that allows significant performance improvements without the use of external memory....
US-7,124,276 Optimizing cache efficiency within application software
The present invention finds the optimum organization of compiled code within an application to ensure maximal cache efficiency. A configuration file specifies...
US-7,124,168 Per CoS memory partitioning
A network device for monitoring a memory partitioned by an identifier can include at least one port configured to receive at least one packet. The at least one...
US-7,123,877 Baseband controller in a wireless local area network
A baseband controller includes a microsequencer that is formed to include special hardware resources and a configuration that facilitates using the ...
US-7,123,460 Methods and systems for reducing power-on failure of integrated circuits
Methods and systems for protecting integrated circuits from power-on sequence currents and for biasing transistors in paths susceptible to power-on sequence...
US-7,123,177 System and method for stabilizing high order sigma delta modulators
A system and method is provided for stabilizing high order sigma delta modulators. The system includes an integrator having a limiter in the feedback path of the...
US-7,123,063 Supply tracking clock multiplier
A circuit for and method of operating a supply tracking clock multiplier is provided. An embodiment of the present invention may permit a less power consuming...
US-7,120,420 Method of creating incentives for establishing hotspot locations
A process of creating incentives for wireless hotspots by a service provider is disclosed. An access point is provided to a wireless hotspot for wireless devices...
US-7,120,412 Calibration circuit for VCO
A phase-locked loop circuit includes an array of selectable capacitors formed within the phase-locked loop circuit to enable the phase-locked loop circuit to...
US-7,120,411 Low noise amplifier (LNA) gain switch circuitry
A circuit is formed to steer current in and out of an inductive load in a manner that enables an amplifier to provide a plurality of gain steps without modifying...
US-7,120,410 LNA gain adjustment in an RF receiver to compensate for intermodulation interference
A Radio Frequency (RF) receiver includes a low noise amplifier (LNA) and a mixer coupled to the output of the LNA. The gain of the LNA is adjusted to maximize...
US-7,120,405 Wide bandwidth transceiver
The wide bandwidth transceiver includes a receiver section, a transmitter section, and a local oscillation module. The receiver section includes a 1.sup.st...
US-7,120,399 High speed CMOS transmit-receive antenna switch
A high-speed CMOS transmit/receive antenna switch includes a first transistor, a second transistor and a parasitic compensation network. The first transistor is...
US-7,120,393 Temperature sensor insensitive to device offsets with independent adjustment of slope and reference temperature
A radio transceiver includes circuitry that enables received RF signals to be down-converted to baseband frequencies and baseband signals to be up-converted to...
US-7,120,319 Data capture apparatus with handwritten data receiving component
A versatile data handling apparatus providing multiple alternatives for inputting data is disclosed. The apparatus includes an array of depressible keys, a...
US-7,120,203 Dual link DVI transmitter serviced by single Phase Locked Loop
A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) to service both a primary link and a secondary...
US-7,120,155 Switch having virtual shared memory
A network of switches having a first switch having a first memory interface and a first expansion port. The network also has an expansion bus having a first...
US-7,120,123 Pre-equalization technique for upstream communication between cable modem and headend
A number of features for enhancing the performance of a cable transmission system in which data is transmitted between a cable modem termination system at a...
US-7,120,117 Starvation free flow control in a shared memory switching device
A shared memory packet switching device includes: a shared memory providing a shared memory space; an input logic unit associated with at least one receive port,...
US-7,119,750 Radio transceiver card communicating in a plurality of frequency bands
A computer apparatus for receiving a removable communication card such as a radio card or a modem card. A radio or modem is self-contained inside a housing of...
US-7,119,726 Error feedback structure for delta-sigma modulators with improved stability
An error feedback circuit includes a first summer receiving an analog input signal and a feedback signal and outputting a summed signal. A quantizer receives the...
US-7,119,631 Off-chip LC circuit for lowest ground and VDD impedance for power amplifier
Off-chip LC circuit for lowest ground and VDD impedance for power amplifier. A novel approach is made by which a chip to PCB (Printer Circuit Board) interface...
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