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Patent # Description
US-7,119,631 Off-chip LC circuit for lowest ground and VDD impedance for power amplifier
Off-chip LC circuit for lowest ground and VDD impedance for power amplifier. A novel approach is made by which a chip to PCB (Printer Circuit Board) interface...
US-7,119,624 Apparatus and method for phase lock loop gain control using unit current sources
A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel...
US-7,119,620 Method and system for constant or proportional to absolute temperature biasing for minimizing transmitter...
In an RF communication system, aspects of constant or proportional to absolute temperature biasing for minimizing transmitter output power variation may comprise...
US-7,119,616 Method and apparatus for a fully differential amplifier output stage
The input stage of the fully differential amplifier output stage is configured in a differential pair configuration with a tail current. The tail current is...
US-7,119,585 Sample and hold circuit based on an ultra linear switch
A sample and hold circuit including a plurality of input signal sampling switches using native NMOS transistors in combination with switched bulk PMOS...
US-7,117,292 Apparatus and method to switch a FIFO between strobe sources
A first-in, first-out (FIFO) unit switches between strobe sources. The FIFO uses a multiplexer to switch between two or more strobes so that different data...
US-7,116,948 High-speed signal power detection circuit
A signal power detector includes an input coupling circuit, a rectifying operational amplifier, a comparator, and a charge pump. The input coupling circuit is...
US-7,116,945 Adaptive radio transceiver with an antenna matching circuit
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local...
US-7,116,742 Timing recovery system for a multi-pair gigabit transceiver
A method and a timing recovery system for generating a set of clock signals in a system which includes a set of subsystems. Each of the subsystems includes an...
US-7,116,729 Trimming of local oscillation in an integrated circuit radio
A method and apparatus for trimming of a local oscillation within a radio frequency integrated circuit (RFIC) includes processing that begins when an RFIC...
US-7,116,666 Switch assisted frame aliasing for storage virtualization
An apparatus and process for relabelling and redirecting at least some of the read transaction data frames and the write transaction write data and transfer...
US-7,116,259 Switching between lower and higher power modes in an ADC for lower/higher precision operations
An analog-to-digital converter (ADC) disposed in a data reception path to convert data from an analog format to a digital format is switched between two or more...
US-7,116,202 Inductor circuit with a magnetic interface
An inductor circuit includes a magnetic interface generator that generates a magnetic interface at a center frequency f.sub.0. The magnetic interface generator...
US-7,116,176 Multiple synthesized clocks from a single clock source
A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input...
US-7,116,163 Buffer circuit
A buffer circuit comprised of two matched stages is provided. The first stage develops a replica voltage that is used in the second stage as the input to a...
US-7,115,952 System and method for ESD protection
An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front...
US-7,114,043 Ambiguous virtual channels
An apparatus comprises a first plurality of buffers configured to store operations belonging to a first virtual channel and a control circuit coupled to the...
US-7,114,024 Apparatus and method for managing memory defects
A method and apparatus for managing defects in a memory, wherein the method includes the steps of testing a plurality of memory locations to determine an...
US-7,114,010 Multi-mode controller
Techniques for controlling and managing network access are used to enable a wireless communication device to selectively communicate with several wireless...
US-7,113,754 High frequency signal power detector
A signal power detector includes an input coupling circuit a rectifying operational amplifier, and a charge pump. The input coupling circuit is operably coupled...
US-7,113,744 Adaptive radio transceiver with a power amplifier
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local...
US-7,113,540 Fast computation of multi-input-multi-output decision feedback equalizer coefficients
Multi-Input-Multi-Output (MIMO) Optimal Decision Feedback Equalizer (DFE) coefficients are determined from a channel estimate h by casting the MIMO DFE...
US-7,113,498 Virtual switch
A method and apparatus for communicating between devices is described. In one embodiment, the method comprises running two or more instances of a switch MAC...
US-7,113,479 Aggregated rate control method and system
A network device, which includes a plurality of network ports, a switching unit, a data classification unit, and a rate control unit, is provided. The plurality...
US-7,113,221 Method and system for converting interlaced formatted video to progressive scan video
Aspects of the invention include a 3:2 pull down detector coupled to a 3:2 cadence processor and a color edge detector coupled to a binder. The binder may be...
US-7,113,004 Sense amplifier with offset cancellation and charge-share limited swing drivers
A sense amplifier adapted to sense an input signal on global bitlines, having an amplifier offset cancellation network and an offset equalization network. The...
US-7,112,998 Method utilizing a one-stage level shift circuit
A system and method for level shifting a core, lower voltage in a one-stage level shift device to produce a higher, driving voltage. The system includes a first...
US-7,112,855 Low ohmic layout technique for MOS transistors
The disclosure relates to a transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first...
US-7,112,853 System for ESD protection with extra headroom in relatively low supply voltage integrated circuits
An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more...
US-7,112,838 Multipurpose metal fill
The present invention adds a plurality of substrate barriers for reducing substrate noise. The barriers, consisting of a plurality of equally sized n-well...
US-7,111,226 Communication decoder employing single trellis to support multiple code rates and/or multiple modulations
Communication decoder employing single trellis to support multiple code rates and/or multiple modulations. A single trellis is employed by the decoder to decode...
US-7,111,208 On-chip standalone self-test system and method
A method and system are disclosed for providing standalone built-in self-testing of a transceiver chip. The transceiver chip includes packet generators for...
US-7,111,127 System for supporting unlimited consecutive data stores into a cache memory
One or more methods and systems of improving the performance of consecutive data stores into a cache memory are presented. In one embodiment, the method...
US-7,111,117 Expansion of RAID subsystems using spare space with immediate access to new space
A method to expand a RAID subsystem from a first array of disk drives to a second array of disk drives. The first array includes a set of data disk drives...
US-7,111,111 Scheme for optimal settings for DDR interface
Methods of optimizing a plurality of numerically controlled delay lines (NCDLS) in a DDR memory controller are presented herein. In one embodiment, a method may...
US-7,111,104 Methods and circuits for stacking bus architecture
A system for connecting multiple repeaters into a single collision domain comprising a first repeater, a second repeater and a stacking bus. The first repeater...
US-7,110,942 Efficient excitation quantization in a noise feedback coding system using correlation techniques
A method of performing an excitation Vector Quantization (VQ) in a Noise Feedback Coding environment involves reorganizing a calculation of an energy of an error...
US-7,110,742 Low noise amplifier with constant input impedance
A low noise amplifier includes an input transistor, an inductor, and a current sink. The input transistor includes a gate, a drain, and a source, wherein the...
US-7,110,736 Analog peak detection circuitry for radio receivers
A receiver portion of a radio includes an analog circuit for determining a peak amplitude in a way that eliminates or reduces the effects of frequency errors...
US-7,110,469 Self-calibrating direct conversion transmitter
A self-calibrating transmitter includes an up-conversion mixing module, summing module, calibration determination module, and a calibration execution module. The...
US-7,110,434 Cancellation of interference in a communication system with application to S-CDMA
A relatively straight-forward implemented, and computationally efficient approach of selecting a predetermined number of unused codes is used to perform weighted...
US-7,110,398 Packet tag for support of remote network function/packet classification
A method and system for creating an ethernet-formatted packet from an upstream DOCSIS packet. The upstream packet is first received along with packet...
US-7,110,309 Memory architecture with single-port cell and dual-port (read and write) functionality
A single-port hierarchical memory structure including memory modules having memory cells; hierarchically-coupled local and global sense amplifiers;...
US-7,110,135 Printer resource sharing in a media exchange network
Systems and methods of printer resource sharing in a communication network are provided. In one embodiment, the system may comprise, for example, at least one...
US-7,110,006 Video, audio and graphics decode, composite and display system
A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section...
US-7,109,947 Methods of generating a magnetic interface
A magnetic interface generator generates a magnetic interface at a center frequency f.sub.0. The magnetic interface generator is a passive array of spirals that...
US-7,109,813 Fast starting on-chip crystal oscillation circuit
A fast starting on-chip crystal oscillation circuit includes a power supply (V.sub.dd) integrated circuit pad, a power return (V.sub.ss) integrated circuit pad,...
US-7,109,801 Low gate oxide stress power amplifier
A power amplifier includes an input transistor, an output transistor, and circuitry. The input transistor includes an input, a first node, and a second node,...
US-7,109,799 Current-controlled CMOS wideband data amplifier circuits
Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance...
US-7,109,798 Method and system for common mode feedback circuitry for RF buffers
For a high frequency buffer, a high frequency output path may be isolated from a low frequency feedback path using a common mode feedback loop. The common mode...
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