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Content addressable memory cell techniques
A content addressable memory cell (10) includes a circuit (20) operating from a predetermined supply voltage (VDD) for storing a first bit of data at a first...
Graphics display system with anti-flutter filtering and vertical scaling
A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video...
Precision tunable voltage controlled oscillation and applications thereof
A precision tunable VCO includes a bias transistor, a first inductor, a second inductor, a first input transistor, a second input transistor, a first capacitor,...
Fine step and large gain range programmable gain amplifier
A programmable gain amplifier with three stages uses fine steps, has a large gain range, and is monotonic. The first stage comprises several amplifiers, each...
Reference buffer with dynamic current control
A method can allow a system to selectively control increasing of a bias source in a reference buffer or decreasing impedance looking into a output of the...
Switchable power domains for 1.2v and 3.3v pad voltages
An integrated circuit includes a core circuit and a buffer circuit. The buffer circuit includes a plurality of input buffers and a plurality of output buffers...
Peripheral bus switch having virtual peripheral bus and configurable host
A peripheral bus switch includes a virtual peripheral bus, a plurality of bridges, and a configurable host bridge. A first bridge operably couples on a first...
Inverse discrete cosine transform supporting multiple decoding processes
The present invention provides an apparatus and method for providing a programmable inverse discrete cosine transform, wherein the transform coefficients are...
Phase locked loop calibration
A method for calibrating a phase locked loop (PLL) includes an open loop test and a closed loop test. The open loop test includes providing an optimal control...
Code puncturing method and apparatus
A method of compressing a puncture mask information is disclosed, the method comprising making a delayed puncture mask by deleting the last k bits of the...
Programmable variable-length decoder
System and method for decoding variable-length codes. A variable-length decoder includes an address generator and a local memory unit. The local memory stores a...
Fully differential, high Q, on-chip, impedance matching section
An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A...
Hardware and software programmable fuses for memory repair
The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable...
Via providing multiple electrically conductive paths
A via provides a plurality of electrical connections between conductors on different layers of a circuit board. The via includes an opening through the circuit...
Variable code rate and signal constellation turbo trellis coded modulation
Variable code rate and signal constellation turbo trellis coded modulation (TTCM) codec. A common trellis is employed at both ends of a communication system (in...
System and method for determining on-chip bit error rate (BER) in a
A test packet generator (225a) within a physical layer device (230) may generate test packets to be communicated over a closed communication path established...
Bus sampling on one edge of a clock signal and driving on another edge
An agent may be coupled to receive a clock signal associated with the bus, and may be configured to drive a signal responsive to a first edge (rising or falling)...
System and method for determining signal consistency
A system and method for determining signal consistency (e.g., in a video signal processing system) are disclosed. Various aspects of the present invention may,...
High output power radio frequency integrated circuit
A high output power radio frequency integrated circuit includes an up conversion module, a plurality of drivers and a plurality of integrated circuit pads. The...
Low loss diversity antenna T/R switch
A low loss transmit/receive switch includes a 1.sup.st antenna capacitive coupling circuit, a 2.sup.nd antenna capacitive coupling circuit, an antenna selection...
Multi-mode band-gap current reference
A multi-mode band-gap current reference includes a band-gap current mode module and an adjustable current source module. The band-gap current module provides a...
Linear phase detector for high-speed clock and data recovery
Methods and apparatus for recovering a clock and data from a data signal. A method provides for receiving a clock signal having a first clock frequency and...
Timing recovery system for a multi-pair gigabit transceiver
A method and a timing recovery system for generating a set of clock signals in a system which includes a set of subsystems. Each of the subsystems includes an...
System and method for recovering and deserializing a high data rate bit
A deserializer that deserializes a high data rate bit stream to extract a set of bits contained therein includes a data sampler, a serial-to-parallel converter,...
Voice and data exchange over a packet based network with AGC
A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a...
Fully integrated tuner architecture
An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front...
Run-level and command split FIFO storage approach in inverse quantization
Presented herein is a run-level split FIFO. According to one embodiment of the present invention, there is presented a method for inverse quantizing. The method...
On-chip differential multi-layer inductor
An on-chip differential multi-layer inductor includes a 1.sup.st partial winding on a 1.sup.st layer, a 2.sup.nd partial winding on the 1.sup.st layer, a...
Method to reduce unwanted oscillations in high speed, high gain or
A system reduces unwanted oscillations in a multiple gigabit per second, high gain amplifier portion. The system includes a power source portion having a...
Design and layout techniques for low parasitic capacitance in analog
A semiconductor device that reduces the parasitic capacitance between a conductive trace and a substrate, and a method of fabricating the same. The semiconductor...
FEC block reconstruction system, method and computer program product for
mitigating burst noise in a...
A system, method and computer program product is provided for mitigating the effects of burst noise on packets transmitted in a communications system. A...
Scan testing mode control of gated clock signals for flip-flops
Circuits and a method to enhance scan testing by controlling clock pulses that are provided to flip-flops within an integrated circuit are provided. An...
Apparatus and method to reduce memory footprints in processor
The present invention provides an apparatus and method to reduce the memory footprint of a processor architecture by structuring processor code to be stored in...
Apparatus for reducing flicker noise in a mixer circuit
A differential mixer includes DC currents that reduce flicker noise in the mixer circuit without increasing local oscillator drive requirements. The differential...
Automatic gain control system and method using multiple local AGC loops
A receiver comprises a first Variable Gain Amplifier (VGA) that amplifies an input signal in accordance with a first gain to produce a first amplified signal....
Highly linear power amplifier and radio applications thereof
A single ended highly linear power amplifier includes a component, a 1.sup.st transistor pair, and a 2.sup.nd transistor pair. The 1.sup.st and 2.sup.nd...
On-chip loop filter for a PLL
An on-chip loop filter includes a 1.sup.st resistor, a 1.sup.st capacitor, a 2.sup.nd capacitor, a 3.sup.rd capacitor, a 2.sup.nd resistor, and a 4.sup.th...
Phase lock loop with cycle drop and add circuitry
Phase locked loops that can adjust the frequency of a clock signal are provided. A transmitter adjusts its data transmission rate in response to the clock signal...
Video encoding and video/audio/data multiplexing device
A buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for proficient division of the...
A digital demodulator includes a mixing section, 1.sup.st and 2.sup.nd digital comb filters, phase locked loop module, and a data recovery module. The mixing...
Switch fabric with memory management unit for improved flow control
A method for controlling a flow of packet data in a memory management unit of a network switch fabric is disclosed. A first portion of a data packet is received...
Access, monitoring, and control of appliances via a media processing
A method and system are provided for accessing, monitoring, and controlling home appliances in a media exchange network by establishing a communication link...
On-chip multiple tap transformer and inductor
An on-chip multiple tap transformer balun includes a 1.sup.st winding and a 2.sup.nd winding having two portions. The 1.sup.st winding is on a 1.sup.st layer of...
Fast starting on-chip crystal oscillation circuit
A fast starting on-chip crystal oscillation circuit includes a (V.sub.dd) IC pad, a (V.sub.ss) IC pad, a 1.sup.st crystal IC pad, a 2.sup.nd crystal IC pad, a...
Antenna diversity structure for use in a radio frequency integrated
A radio frequency integrated circuit includes a power amplifier, a low noise amplifier, a first transformer balun, and a second transformer balun. The power...
Seal ring for integrated circuits
The present invention is directed to a seal structure and a method for forming a seal structure for a semiconductor die. An elongate region which is electrically...
Close two constituent trellis of a turbo encoder within the interleave
Close two constituent trellis of a turbo encoder within the interleave block. The state of a multi-state encoder is forced to a known/predetermined state at the...
Addition circuit for accumulating redundant binary numbers
An addition circuit for producing a sum of four redundant binary numbers includes a 4:2 compression adder for receiving each of the operand fields of the four...
Phase based system and method for determining signal consistency
A phase based system and method for determining signal consistency (e.g., in a video signal processing system). Various aspects of the present invention may, for...
System and method for shuffling mapping sequences
A sequence mapping circuit and method for digital audio circuits generates a pulsed output. Over time, the mapping circuit generates pulses with a substantially...