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Patent # Description
US-7,050,778 Direct conversion turner
A direct conversion tuner down-converts television signals, cable signals, or other signals directly from an RF frequency to an IF frequency and/or baseband,...
US-7,050,777 Methods and circuitry for reducing intermodulation in integrated transceivers
Methods and circuitry reduce adverse impacts of intermodulation and optimize performance of integrated circuits that include two or more oscillator circuits on...
US-7,050,516 System and method for periodic noise avoidance in data transmission systems
A system for periodic noise avoidance including a timing discriminator receiving an input signal from a communications channel. The input signal includes data...
US-7,050,501 Digital noise reduction techniques
A preprocessor system (10) reduces random noise in video pixels by providing a memory (19) arranged to store first pixels processed during a first time period. A...
US-7,050,431 Linked network switch configuration
A network device includes a first switch, a second switch, address resolution logic (ARL), and a CPU. The first and second switch having a groups of ports which...
US-7,050,430 Gigabit switch with fast filtering processor
A network switch for network communications includes at least one data port interface supporting a plurality of data ports transmitting and receiving data. A CPU...
US-7,050,420 System for maintaining synchronization between multiple asynchronous communication links
An apparatus for maintaining synchronization with a plurality of asynchronous communication links includes a first counter that generates a first local network...
US-7,049,990 Single loop feed-forward modulator with summing flash quantizer and multi-bit feedback
A sigma-delta modulator includes a summing junction that receives an input signal. A plurality of integrators are arranged in series, the integrators output an...
US-7,049,882 Transmitter IF section and method enabling IF output signal amplitude that is less sensitive to process,...
Embodiments of the invention enable generation of an IF output signal amplitude that is less sensitive to process voltage and temperature than conventional...
US-7,049,868 System and method for compensating for supply voltage induced clock delay mismatches
Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog...
US-7,049,860 Method and circuit for controlling a resistance of a field effect transistor configured to conduct a signal...
The present invention relates to a replica network for linearizing switched capacitor circuits. A bridge circuit with a MOSFET resistor disposed in a resistor...
US-7,049,856 High speed peak amplitude comparator
Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow...
US-7,049,851 Decoder circuit
A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first...
US-7,049,848 Linear buffer
A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output...
US-7,049,204 High density metal capacitor using via etch stopping layer as field dielectric in dual-damascence interconnect...
A metal-insulator-metal (MIM) capacitor is made according to a copper dual-damascene process. A first copper or copper alloy metal layer if formed on a...
US-7,047,428 Method and apparatus for performing wake on LAN power management
A single integrated circuit includes logic that supports 10BASE-T, 100BASE-T and 1000BASE-T transceiver functionality. The invention implements power management...
US-7,047,381 System and method for providing one-time programmable memory with fault tolerance
Systems and methods that provide a one-time programmable (OTP) memory with fault tolerance are provided. In one example, the OTM memory may include a data...
US-7,046,989 Controlling and enhancing handoff between wireless access points
A process of maintaining access information between wireless hotspots is disclosed. A logon request from a wireless portable device is received by a first access...
US-7,046,796 System and method for providing power over a home phone line network
A system and method is provided for supplying power over a home phone line network in a manner that is interoperable with other voice and data services operating...
US-7,046,773 System and method for preventing telephone line blocking by a modem
A modem includes a Digital Access Arrangement (DAA) Circuit and modem software that is executed by a processor. When the DAA Circuit detects that the modem...
US-7,046,752 Adaptive electronic transmission signal cancellation apparatus for full duplex communication
An adaptive electronic transmission signal cancellation circuit for separating transmit data from receive data in a bidirectional communication system operating...
US-7,046,679 Gigabit switch with frame forwarding and address learning
A network switch and a method thereof for network communications include a first data port interface and a second data port interface supporting a data port...
US-7,046,664 Point-to-multipoint network interface
A point-to-multipoint network interface is provided that is simpler and less costly to implement than conventional Ethernet switches. The interface includes a...
US-7,046,097 Highly stable integrated time reference
An integrated oscillator that may be used as a time clock includes circuitry that oscillates about an RC time constant, which RC time constant is adjustable to...
US-7,046,068 CMOS-based receiver for communications applications
A receiver and receiver front end having multiple independent differential inputs, multiple independent differential low-noise amplifiers, and two sets of...
US-7,046,014 ATE measurement technique for comparator threshold voltage
A system and a method for testing a comparator include generating two triangular waveform segments having the same period and different amplitudes, inputting the...
US-7,043,618 System for memory access in a data processor
A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of...
US-7,042,939 System for, and method of, processing quadrature amplitude modulated signals
Analog signals encoded with quadrature amplitude modulation (QAM) pass through a coaxial cable at a particular baud rate. These signals have a carrier frequency...
US-7,042,863 Efficient time-division multiplexed addressing protocol
A method and apparatus for communicating within a system including a master unit and one or more slave units is disclosed herein. A member address, corresponding...
US-7,042,843 Algorithm for time based queuing in network traffic engineering
The present invention provides a method for prioritizing packet flows within a switching network. The method includes the steps of receiving packets at an input...
US-7,042,381 Delay equalized Z/2Z ladder for digital to analog conversion
A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors...
US-7,042,375 System and method using dither to tune a filter
A system and method is used to tune filters, for example, analog filters in a sigma-delta modulator ADC. A known dither signal is used, for example a digital...
US-7,042,302 VCO with power supply rejection enhancement circuit
An oscillating circuit having a noise reduction circuit is disclosed. The noise reduction circuit is coupled to the current source for the oscillating circuit....
US-7,042,271 Resistor compensation apparatus
A compensation apparatus maintains an effective resistance of one or more resistors in a circuit by associating an adjustable resistor circuit to each resistor....
US-7,039,776 Patch memory system for a ROM-based processor
An embedded ROM-based processor system including a processor, system memory, a programmable memory, a data selector and a patch controller. The system memory...
US-7,039,748 Memory mapped I/O bus selection
A mechanism and method for redefining an application specific integrated circuit's I/O bus structure in real-time. The mechanism includes an address map block, a...
US-7,039,384 Low power band-gap current reference
A low power supply band-gap current reference includes a 1.sup.st P-N junction device, a 2.sup.nd and P-N junction device, a 1.sup.st current source, a 2.sup.nd...
US-7,039,382 DC offset calibration for a radio transceiver mixer
A mixer for a radio transceiver includes a commutating mixer switch having a first differential input port coupled to a DC offset cancellation path. The first...
US-7,039,381 On-chip differential inductor and applications thereof
An on-chip differential inductor includes a 1.sup.st interwound winding having a substantially octagonal shape, or rectangular octagonal shape, and a 2.sup.nd...
US-7,039,102 Highly integrated asymmetric digital subscriber line (ADSL) circuit
An asymmetric digital subscriber line (ADSL) transceiver chip is provided that includes a single integrated circuit (IC) substrate to host the circuit and an...
US-7,039,010 Optimized data path structure for multi-channel management information base (MIB) event generation
The present invention provides for handling data flow within a network device, which includes a cycle timing module, a division module, an assignment module, and...
US-7,038,607 Modulation circuit having improved performance in the audio band
A modulator circuit receives a modulator input signal and produces a mapper output signal. The modulator circuit includes a filter circuit that generates an...
US-7,038,545 Gigabit ethernet transceiver with analog front end
Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain...
US-7,038,533 Gigabit ethernet transceiver with analog front end
Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain...
US-7,038,516 Current-controlled CMOS logic family
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process...
US-7,038,510 Phase adjustment method and circuit for DLL-based serial data link transceivers
A delay locked loop circuit with a first flip flop driven by a 0.degree. clock and receiving the input data. A second flip flop by a 180.degree. clock and...
US-7,038,495 Low jitter high speed CMOS to CML clock converter
Provided is a circuit to convert input CMOS level signals having a predetermined duty cycle to CML level signals having a higher duty cycle. The circuit includes...
US-7,038,487 Multi-function interface
A multi-function interface includes a digital interface module and a configurable output impedance module. The digital interface module is operably coupled to...
US-7,038,312 Die-up ball grid array package with attached stiffener ring
An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate...
US-7,036,001 Vector processing system
A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said...
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