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Bluetooth access code assisted initial DC estimation and frame
A system for calculating DC offset and achieving frame detection is described. In one embodiment, the present invention includes an electronic device with an...
Parallel concatenated code with soft-in soft-out interactive turbo decoder
A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may...
Jitter suppression techniques for laser driver circuits
Driver circuits of the present invention provide current to drive laser diodes. The output current of the driver circuit includes a data signal and a low...
A system and method for detecting and removing tones from an incoming communications channel that may also carry other signals such as, for example, voice is...
Linked network switch configuration
A network device having a plurality of ports including address resolution logic (ARL), a first switch, a second switch, and a CPU. The first and second switches...
Transceiver method and signal therefor embodied in a carrier wave for a
frame-based communications network
A method and signal therfor embodied in a carrier wave for sending information from transmit stations to receive stations over a transmission medium of a...
Linked network switch configuration
A network device includes a first switch, a second switch, and a CPU. The first and second switches each include a group of ports numbered by a numbering scheme,...
Communication timing coordination techniques
A communication unit (30) arranged to send transmit data includes a receiver (32) arranged to recover input data transmitted at a downstream transfer rate in...
Method and apparatus for the synchronization of multiple cable modem
termination system devices
A plurality of CMTS devices are linked together and synchronized to facilitate communication between the respective CMTS devices and respective downstream cable...
System and method for communicating over a wireless time-division duplex
According to the present invention, the bandwidth of a TDD channel is increased where multiple slave devices communicate with a master device over the channel....
Multi-rate, multi-port, gigabit Serdes transceiver
A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to...
Asynchronously-resettable decoder with redundancy
A decoder providing asynchronous reset, redundancy, or both. an asynchronously-resettable decoder with redundancy. The decoder has a synchronous portion,...
Method of operating a video decoding system
A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core...
Method and apparatus for reception of terrestrial digital television
A digital television signal is intercepted by a plurality of antennas to produce a corresponding plurality of input signals. The antennas have different...
Printed dipole antenna
A printed dipole antenna includes a metal trace having first type sections and second type sections, wherein currents within the first type sections ...
Multi-tuner receivers with cross talk reduction
Multi-tuner receivers with cross talk reduction are disclosed. In one embodiment, a multi-tuner receiver with cross talk reduction includes a low noise...
Apparatus, system, and method for amplifying a signal, and applications
An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is...
VGA-CTF combination cell for 10 Gb/s serial data receivers
An input processing circuit includes a first and second input transistors for receiving a differential pair of first and second input signals, respectively. At...
Apparatus for frequency dividing a master clock signal by a non-integer
A frequency dividing circuit divides a master clock frequency by a non-integer factor to provide an output clock signal whose frequency is equal to the frequency...
Method of manufacturing high Q on-chip inductor
A high Q on-chip inductor includes a primary winding and an auxiliary winding that is coupled to receive a proportionally opposite representation of an input of...
System and method for implementing a flexible top level scan architecture
using a partitioning algorithm to...
A method and system are disclosed for balancing a plurality of flip-flops across a number of global scan chains in a design of a digital integrated circuit chip....
Efficient design to calculate extrinsic information for soft-in-soft-out
Efficient design to calculate extrinsic information for Soft-In-Soft-Out (SISO) decoder. A design provides for very efficient performing extrinsic value...
Generalized convolutional interleaver/de-interleaver
A memory-efficient convolutional interleaver/de-interleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their...
System and method for executing hybridized code on a dynamically
configurable hardware environment
A system and method for executing previously created run time executables in a configurable processing element array is disclosed. In one embodiment, this system...
Radio frequency transmitter having translational loop phase equalization
A Radio Frequency RF transmitter includes a translational loop architecture that supports non-constant envelope modulation types and includes by adjusting the...
Adaptive radio transceiver with a local oscillator
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local...
Deterministic distortion insensitive adaptive receiver using decision
A technique has been developed whereby an adaptive receiver may employ decision updating in a manner insensitive to RBS. One realization achieves nearly-ideal...
Digital to analog converter with time dithering to remove audio tones
A Digital-to-Analog-Converter (DAC) includes an interpolation filter, a modulator, and a time dither clock reduction circuit. The interpolation filter receives...
High-speed stats gathering in a network switch
A network switch includes a data port for communicating with a data network, and a statistics counter coupled to the data port for monitoring operational...
State-delayed technique and system to remove tones of dynamic element
A filter structure used with a dynamic element matching encoder for a sigma-delta digital-to-analog converter is presented. A sampled input sequence having...
Systems and methods for auto gain control in Bi-CMOS digital to analog
The accuracy of output power in a digital-to-analog converter (DAC) is critical in certain applications. When bi-CMOS technology is used to implement a DAC, a...
Circuit and method for controlling gain in an amplifier
A circuit is provided for controlling the gain of an amplifier, such as an amplifier that may be used in telecommunication devices. The circuit includes an...
Biasing scheme for low supply headroom applications
Methods and apparatus for improving the current matching within current mirror circuits in applications such as low voltage integrated circuits. Embodiments of...
Method and apparatus for adaptive power management of memory subsystem
A method and apparatus are disclosed for performing adaptive memory power management in a system employing a CPU and a memory subsystem. A CPU throttle control...
A method for transferring data, between a first device and second device in a core processor including a data cache, comprising the steps of, when said first...
Source triggered transaction blocking
A system may include at least a first agent and a second agent, and the first agent may be coupled to receive a block signal generated by the second agent. The...
A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver...
Technique for improving modulation performance of translational loop RF
A transmit signal generated by the baseband processor in a translational loop type RF transmitter is "pre-distorted" so as to counter act magnitude distortion...
Pipeline architecture for multi-slot wireless link processing
A wireless communication device processes N Radio Frequency (RF) bursts contained within N slots of a digital communications time divided frame, wherein N is a...
Viterbi decoding with channel and location information
A method for exploiting location information inherent in the location of points within a transmitted signal constellation. A common method for assigning weights...
Timing recovery using the pilot signal in high definition TV
Improved carrier recovery and symbol timing systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system is disclosed. Carrier and...
Fast computation of decision feedback equalizer coefficients
Optimal Decision Feedback Equalizer (DFE) coefficients are determined from a channel estimate h by casting the DFE coefficient problem as a standard recursive...
Method and system for a multi-rate analog finite impulse response filter
Provided are a system and method for implementing a multirate analog finite impulse response (FIR) filter. A system of the present invention includes a modulator...
Multiple layer inductor and method of making the same
A multiple layer inductor has a first spiral conductive pattern disposed on a first surface; a second spiral conductive pattern disposed on a second surface; a...
System and method for a programmable gain amplifier
Provided is system for an improved programmable gain amplifier (PGA). The system includes an amplifier and a first gain control mechanism. The first gain control...
Method and apparatus for reliable pulse event detection
A circuit for detecting asynchronous events includes a first event detection latch; and a second event detection latch coupled to the first event detection...
Method and apparatus for detection and classification of impairments on a
RF modulated network
A method and apparatus for detecting and classifying RF impairments on the upstream path of a communication system is provided. The detection system detects...
Generalized convolutional interleaver/deinterleaver
A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their...
Efficient address generation for interleaver and de-interleaver
Efficient address generation for interleaver and de-interleaver. The present invention performs interleaving and de-interleaving, at opposite ends of a...
Network interface using programmable delay and frequency doubler
A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an...