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Patent # Description
US-7,023,934 Method and apparatus for min star calculations in a map decoder
Method and apparatus for Min star calculations in a Map decoder. Min star calculations are performed by a circuit that includes a first circuit that performs an...
US-7,023,868 Voice gateway with downstream voice synchronization
A network gateway is configured to facilitate on line and off line bi-directional communication between a number of near end data and telephony devices with far...
US-7,023,371 Method and apparatus for an image canceling digital-to-analog converter (DAC)
A method and apparatus for an image canceling digital-to-analog converter is disclosed. Up-sampling and noise shaping is used to produce a stream of digital...
US-7,023,185 Power supply for controlled parallel charging and discharging of batteries
A power supply and switching technique is provided that utilizes a first battery and a second battery to charge a load. The power supply includes a first...
US-7,020,831 Pipelined add-compare-select circuits and methods, and applications thereof
Digital communications devices having high-speed add-compare-select circuits, and methods for designing the same. The add-compare-select circuits include logic...
US-7,020,812 System and method for detection and recovery of false synchronization using packet header information
Presented herein are system(s), method(s), and apparatus f or detecting and recovering from false synchronization. When incorrect checksums are encountered,...
US-7,020,449 Fast settling variable gain amplifier with DC offset cancellation
A variable gain amplifier includes circuit elements that may be partially powered down during transmit modes of operation and that may be powered back up...
US-7,020,220 Digital estimation and correction of I/Q mismatch in direct conversion receivers
An IQ receiver includes an estimator/compensator module to determine and correct IQ mismatch errors between the I and Q channels of the IQ receiver. The...
US-7,020,210 Inter-device adaptable interfacing clock skewing
Inter-device adaptable interfacing clock skewing. The invention is operable in either one of both of a transmit mode and a receive mode to perform skewing of a...
US-7,020,188 Multi-tone transmission
A multi-tone modem processes an input data stream 10 and uses an inverse Fourier transform 24 to produce a stream of multi-tone symbols 26 fed to an analogue...
US-7,020,166 Switch transferring data using data encapsulation and decapsulation
A method for encapsulating and decapsulating information into a data packet being transmitted through a plurality of switches. The method has the steps of...
US-7,020,139 Trunking and mirroring across stacked gigabit switches
A method of handling data packets in a network switch is disclosed. The method includes placing incoming packets into an input queue and applying the input data...
US-7,020,137 Network switching architecture with fast filtering processor
A network switch for network communications includes a first data port interface supporting a plurality of data ports transmitting and receiving data at a first...
US-7,020,099 Apparatus for, and method of, reducing noise in a communications system
A communication line having a plurality of twisted wire pairs connects a plurality of transmitters, one transmitter at each end of each twisted wire pair, with a...
US-7,019,679 Multiplexer with low parasitic capacitance effects
A differential multiplexer includes a plurality of multiplexing circuits. Each multiplexing circuit inputs a corresponding differential input signal including a...
US-7,019,598 Integrated VCO having an improved tuning range over process and temperature variations
An integrated VCO having an improved tuning range over process and temperature variations. There is therefore provided in a present embodiment of the invention...
US-7,019,597 Method and circuitry for implementing a differentially tuned varactor-inductor oscillator
The present invention generally relates to voltage-controlled oscillators. More specifically, the present invention relates to method and circuitry for...
US-7,019,591 Gain boosted operational amplifier having a field effect transistor with a well biasing scheme
A biasing scheme for a MOSFET that mitigates the MOSFET body effect. The biasing scheme can be realized replicating the voltage at the source terminal of a...
US-7,019,565 Methods and systems for fully differential frequency doubling
Methods and systems for fully differential frequency doubling include receiving a differential input signal having a first frequency, generating a non-inverted...
US-7,017,106 Low density parity check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses
Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated...
US-7,017,098 Built-in self-test for multi-channel transceivers without data alignment
A method and device for testing multi-channel transceivers in an integrated circuit is provided. More specifically, the present invention relates to a method and...
US-7,017,032 Setting execution conditions
A method for setting indicators in a control store of a computer system for conditionally performing operations, comprises providing a control store setting...
US-7,017,020 Apparatus and method for optimizing access to memory
A method and apparatus for optimizing access to memory, wherein the method includes the steps of receiving a first request for access to a memory, receiving at...
US-7,016,613 Linear half-rate phase detector and clock and data recovery circuit
Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate,...
US-7,016,449 Timing recovery and frequency tracking system and method
A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at...
US-7,016,415 Modifying motion control signals based on input video characteristics
A motion detector (300) detects motion of images represented by video pixels. A first motion detector (320) is arranged to generate first motion signals (S)...
US-7,016,296 Adaptive modulation for fixed wireless link in cable transmission system
Methods and systems for communicating on a wireless channel are provided which enable subscribers that share the channel to transmit using different modulation...
US-7,015,928 Graphics display system with color look-up table loading mechanism
A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video...
US-7,015,750 Method for lowering noise and providing offset correction in a transimpedance amplifier
A system for receiving signals (e.g., optical signals) includes an input device, an amplification device, and a feedback device. The amplification device...
US-7,015,722 Current-controlled CMOS circuits with inductive broadbanding
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic with inductive broadbanding fabricated in...
US-7,015,545 Split source RF MOSFET device
An RF MOS transistor having improved AC output conductance and AC output capacitance includes parallel interdigitated source and drain regions separated by...
US-7,013,437 High data rate differential signal line design for uniform characteristic impedance for high performance...
Provided is an apparatus that includes an integrated circuit (IC) mounted on a chip carrier. The IC has one or more differential pair circuits coupled thereto...
US-7,013,402 System and method for sequencing of signals applied to a circuit
A circuit for applying power to mixed mode integrated circuits in a predefined sequence. The circuit includes a first circuit powered by a first voltage and a...
US-7,013,138 Local area network having multiple channel wireless access
A communication network having at least one access point supports wireless communication among a plurality of wireless roaming devices via a first and a second...
US-7,013,118 High speed operational amplifier design
A radio receiver portion of a transceiver includes a differential amplifier that is used to provide a fast response. A pair of input MOSFETs of the differential...
US-7,013,117 Analog power detection for gain control operations
A method and apparatus for dynamically controlling a programmable gain amplifier (PGA) in a radio receiver to provide a plurality of gain steps thereby providing...
US-7,012,983 Timing recovery and phase tracking system and method
A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at...
US-7,012,975 Method and apparatus for performing calculations for forward (alpha) and reverse (beta) metrics in a map decoder
Method and apparatus for performing calculations for forward (alpha) and reverse (beta) metrics in a map decoder. The method includes using a min star (min*)...
US-7,012,957 High performance equalizer having reduced complexity
An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP)...
US-7,012,559 Hierarchical parallel pipelined operation of analog and digital circuits
A hierarchical parallel pipelined circuit includes a first stage with a plurality of sampling circuits and a plurality of corresponding analog or digital...
US-7,012,487 Transconductance device employing native MOS transistors
A system on chip such as a radio receiver has reduced suceptibility to voltages in the bulk silicon by using gyrator elements in the receiver with each gyrator...
US-7,012,474 System and method generating a delayed clock output
The system and method generates two clock signals, one with a 2 ns delay with respect to the other, from a single PLL to enable a RGMII.
US-7,012,464 Method and circuit for a dual supply amplifier
A circuit and method for bridging an analog signal between two integrated circuits operating at different supply voltages. The circuit is a two stage fixed gain...
US-7,010,708 Method and apparatus for adaptive CPU power management
A method and apparatus are disclosed for performing adaptive run-time power management in a system employing a CPU and an operating system. A CPU cycle tracker...
US-7,010,557 Low power decimation system and method of deriving same
A decimation system comprising a plurality, L, of cascaded Finite Impulse Response (FIR) decimation filters. Each decimation filter has a transfer function of...
US-7,010,535 Binary search engine and method
A network device including a memory, a queue management unit, a memory management unit, and a search switching unit. The memory includes a plurality of memory...
US-7,010,279 Radio frequency integrated circuit electro-static discharge circuit
The radio frequency integrated circuit (RFIC) electrostatic discharge (ESD) circuit includes a transformer balun, an impedance matching circuit and a clamping...
US-7,010,062 System and method for multi-carrier modulation
A method of compensating for carrier frequency and phase errors of a received multi-carrier modulated signal. The received multi-carrier signal including...
US-7,010,028 System and method for rapid generation of low par Q-mode signals
In a data communication system, a transmitter of an ADSL modem uses a PRBS generator to generate a plurality of ADSL signals. The transmitter computes the Peak...
US-7,009,985 Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in...
A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each...
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