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Patent # Description
US-7,009,985 Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in...
A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each...
US-7,009,973 Switch using a segmented ring
A network switch is disclosed having at least one data port interface for receiving data and at least one link interface configured to transmit the data between...
US-7,009,968 Gigabit switch supporting improved layer 3 switching
A network switch for network communications is disclosed. The switch includes a first data port interface, supporting at least one data port transmitting and...
US-7,009,933 Traffic policing of packet transfer in a dual speed hub
A system for policing traffic of packet transfer in a hub. The system includes a first circuit and a second circuit and a first data line connecting the first...
US-7,009,891 System and method for one-time programmed memory through direct-tunneling oxide breakdown
A one-time programming memory element, capable of being manufactured in a 0.13 .mu.m or below CMOS technology, having a capacitor, or transistor configured as a...
US-7,009,883 Automatic programming time selection for one time programmable memory
A method of programming a memory includes the steps of attempting to program a bit at a designated address for a predetermined time; testing the bit to see if it...
US-7,009,832 High density metal-to-metal maze capacitor with optimized capacitance matching
A capacitor including a first and second component capacitor structure disposed on a substrate. A component capacitor structure includes an upright arm, a...
US-7,009,542 System and method for spectral shaping of dither signals
An improved dither generation circuit and method for digital audio circuits uses a high-pass filter to reduce the energy contained in the audio band of the...
US-7,009,115 Optimization of routing layers and board space requirements for a ball grid array package
A method, system, and apparatus for optimizing routing layers and board space requirements for a ball grid array package is described. The ball grid array...
US-7,007,163 Methods and apparatus for accelerating secure session processing
Methods and apparatus are provided for an entity such as a CPU to efficiently call a cryptography accelerator to perform cryptographic operations. A function...
US-7,007,031 Memory system for video decoding system
System and method of data unit management in a decoding system employing a decoding pipeline. Each incoming data unit is assigned a memory element and is stored...
US-7,006,806 System and method for SAP FM demodulation
Certain embodiments of the present invention provides a system and method for SAP FM demodulation. The system includes a bandpass filter for isolating the SAP...
US-7,006,563 Decision feedback equalizer for minimum and maximum phase channels
This invention describes an apparatus and method to improve the performance of a decision feedback equalizer (DFE) for time-varying multi-path channels. For...
US-7,006,535 Method and system for providing time offset to minislot clock and count in headend devices
A method and system for allocating an initial maintenance request (IMR) for an upstream channel in a communications system, wherein the communication system...
US-7,006,152 System and method for providing picture-in-picture timebase management
Systems and methods that provide picture-in-picture timebase management are provided. In one example, a method may include the steps of sending a first video...
US-7,005,902 Charge pump including a feedback device for use in a phase-locked loop
A charge pump circuit includes a high-swing transconductance amplifier. A high input swing transconductance is provided in a negative feedback loop of the charge...
US-7,005,899 Frequency division/multiplication with jitter minimization
A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency...
US-7,005,898 Programmable divider with built-in programmable delay chain for high-speed/low power application
A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock...
US-7,005,892 Circuit technique for high speed low power data transfer bus
A high speed low power data transfer bus circuit that reduces bus power consumption by imposing a limited, controlled voltage swing on the associated data bus....
US-7,005,753 Optimization of routing layers and board space requirements for a ball grid array land pattern
A method, system, and apparatus for optimizing routing layers and board space requirements for a ball grid array land pattern is described. The land pattern...
US-7,005,737 Die-up ball grid array package with enhanced stiffener
An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate...
US-7,004,395 Multi-level hierarchical radio-frequency communication system
Portable measuring devices which communicate by low power transceivers through a communication controller with a printer device collect weight and size data on...
US-7,003,718 Memory-based shuffle-exchange traceback for gigabit Ethernet transceiver
A decoder having a memory structure which receives and stores potential symbols, with each of the potential symbols having a unique pointer associated therewith....
US-7,003,713 Variable Hamming error correction for a one-time-programmable-ROM
A one-time-programmable (OTP) module includes OTP memory and OTP input/output (I/O) that performs error correction operations. The OTP module may be used in a...
US-7,003,631 System having address-based intranode coherency and data-based internode coherency
A system comprises a plurality of nodes, each node comprising one or more coherent agents coupled to an interconnect. Ownership of a coherency block accessed by...
US-7,003,615 Tracking a non-posted writes in a system using a storage location to store a write response indicator when the...
An apparatus includes a storage location and a write monitor circuit coupled to the storage location. The storage location is configured to store a write...
US-7,002,982 Apparatus and method for storing data
A method and apparatus for storing data, the method including the steps of generating a glitchless fractional clock pulse in a circuit and transmitting the...
US-7,002,602 Apparatus and method for blending graphics and video surfaces
A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video...
US-7,002,595 Processing of color graphics data
A method is provided of processing data representing pixel color having a luminance component and color difference components. The data is divided into first and...
US-7,002,497 Methods and systems for digital dither
Methods and systems for applying digital dither in data converters, such as delta-sigma data converters. In one embodiment, an analog signal from a first path of...
US-7,002,494 Low memory and MIPS efficient technique for decoding Huffman codes using multi-stage, multi-bits lookup at...
Present herein is a low memory and MIPS efficient technique for decoding Huffman codes using multi-stage, multi-bits lookup at different levels. A binary tree is...
US-7,002,405 Linear low noise transconductance cell
A low noise transconductance cell includes a resistor and a differential circuit pair having two equivalent half-circuits. Each half-circuit includes a feedback...
US-7,002,403 Transconductance/C complex band-pass filter
A complex filter such as the channel select filter in a radio transceiver is implemented using a transconductance/C topology to benefit from the ability to tune...
US-7,002,402 Method of producing a desired current
A current source DAC has calibration of the current sources used for providing the analog output. There are two outputs, one of which provides the output current...
US-7,002,383 Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL)
A method and apparatus are disclosed for efficiently doubling a first frequency of a first clock signal. A second clock signal at a second frequency is generated...
US-7,002,379 I/O circuit using low voltage transistors which can tolerate high voltages even when power supplies are powered off
An apparatus for providing bias voltages for input/output (I/O) connections on low voltage integrated circuits. In one embodiment, the invention comprises an I/O...
US-7,002,360 System and method for measuring the thickness or temperature of a circuit in a printed circuit board
System for measuring a thickness of a circuit component on a printed circuit board (PCB). The system includes a first circuit, a power plane, a power strip, a...
US-7,002,238 Use of a down-bond as a controlled inductor in integrated circuit applications
A Radio Frequency (RF) device includes a semi conductive die and a package in which the semi conductive die mounts. The semi conductive die includes a first...
US-7,000,206 Timing path detailer
A method (and a computer accessible medium comprising one or more instructions which, when executed, implement the method) is contemplated. At least a first...
US-7,000,076 Random generator
A random number generator circuit includes a primary circuit configured to generate a value within a first range and a secondary circuit configured to generate a...
US-7,000,031 Method of providing synchronous transport of packets between asynchronous network nodes in a frame-based...
A method of providing synchronous transport of packets between asynchronous network nodes. An asynchronous network node capable of transmitting and receiving...
US-6,999,744 Measurement of local oscillation leakage in a radio frequency integrated circuit
The measuring of local oscillation leakage in radio frequency integrated circuits (RFICs) begins by concurrently enabling a transmitter portion and a receiver...
US-6,999,735 Digital high frequency power detection circuit
A digital high frequency power detection circuit includes a peak detecting circuit and a peak computing circuit. The peak detecting circuit is operably coupled...
US-6,999,455 Hardware assist for address learning
A switch using indicators for address learning. The switch has a first activator configured to control a first indicator to indicate when a source address needs...
US-6,999,414 System and method for combining requests for data bandwidth by a data provider for transmission of data over an...
A method and system for combing requests for data bandwidth by a data provider for transmission of data over an asynchronous communication medium is provided. A...
US-6,998,922 Phase locked loop modulator calibration techniques
A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then...
US-6,998,921 Method for avoiding avalanche breakdown caused by a lateral parasitic bipolar transistor in an MOS process
A power amplifier includes a transconductance stage, a cascode stage, and a connector. The transconductance stage is operable to receive an input voltage signal...
US-6,998,885 Apparatus and method for delay matching of full and divided clock signals
A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference...
US-6,998,877 High speed differential signaling logic gate and applications thereof
A high-speed differential signaling logic gate includes a 1.sup.st input transistor, 2.sup.nd input transistor, complimentary transistor, current source, a...
US-6,998,709 RFIC die-package configuration
A RFIC includes a die and a package. The die contains a radio frequency (RF) input/output (I/O) section, an RF-to-baseband conversion section, and a baseband...
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