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Patent # Description
US-6,985,015 Sub-micron high input voltage tolerant input output (I/O) circuit
A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the...
US-6,985,014 System and method for compensating for the effects of process, voltage, and temperature variations in a circuit
A system and method for compensating for process, voltage, and temperature variations in a circuit is provided. A system includes an inverter having an input...
US-6,983,017 Method and apparatus for implementing reduced memory mode for high-definition television
A method and apparatus are provided for implementing an enhanced reduced memory mode (RMM) of decoding HDTV MPEG-2 video stream. In one instance, the RMM mode is...
US-6,982,727 System and method for providing graphics using graphical engine
Systems and methods that provide graphics using a graphical engine are provided. In one example, a system may provide layered graphics in a video environment....
US-6,982,659 Method and apparatus for iterative decoding
Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative...
US-6,982,604 CDR lock detector with hysteresis
A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to...
US-6,982,602 Low voltage input current mirror circuit and method
A low voltage current mirror circuit (also referred to as a bias circuit) for establishing a plurality of bias voltages from an input current supplied to an...
US-6,982,583 Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process...
US-6,981,074 Descriptor-based load balancing
A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet...
US-6,981,058 System and method for slot based ARL table learning with concurrent table search using write snoop
A network device including at least one network port, a clock, address resolution logic (ARL) tables, and address resolution logic. The clock generates a timing...
US-6,980,951 Noise feedback coding method and system for performing general searching of vector quantization codevectors...
A method of searching a plurality of Vector Quantization (VQ) codevectors for a preferred one of the VQ codevectors to be used as an output of a vector quantizer...
US-6,980,789 Divider module for use in an oscillation synthesizer
A divider module for use in an oscillation synthesizer includes a plurality of flip-flops and a logic circuit. The plurality of flip-flops is interoperably...
US-6,980,774 Radio frequency integrated circuit
A radio frequency (RF) integrated circuit (IC) includes a local oscillation module, analog radio receiver, analog radio transmitter, digital receiver module,...
US-6,980,601 Rate adaptation and parameter optimization for multi-band single carrier transmission
A method for enhancing the bit rate and/or margin at which quadrature amplitude modulation (QAM) communication is performed over multiple bands of a...
US-6,980,528 Voice and data exchange over a packet based network with comfort noise generation
A signal processing system which discriminates between voice signal and data signals modulated by a voiceband carrier. The signal processing system includes a...
US-6,980,161 Radio transceiver card communicating in a plurality of frequency bands
A card includes in a radio transceiver that communicates in first and second frequency bands. First and second antennas are in the card and are coupled to the...
US-6,980,145 System and method for noise cancellation in a signal processing circuit
A system and method for noise cancellation in a signal-processing circuit (e.g., an analog-to-digital converter circuit). Various aspects of the present...
US-6,980,053 Adaptable voltage control for a variable gain amplifier
A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain...
US-6,979,608 Method of manufacturing an on-chip inductor having improved quality factor
An on-chip inductor may be fabricated by creating at least one dielectric layer, creating at least one conductive winding on the at least one dielectric layer...
US-6,978,426 Low-error fixed-width modified booth multiplier
A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth...
US-6,978,216 Testing of integrated circuits from design documentation
One or more methods and systems of validating the operation of one or more register designs are presented. In one embodiment, the system utilizes a processor, an...
US-6,977,658 System for and method of performing an opacity calculation in a 3D graphics system
A system, device and method are disclosed for predicting the opacity of primitives used to produce an image using one or more equations, prior to producing an...
US-6,977,531 RF signal peak detector
A method for determining a peak value of a radio frequency (RF) signal begins by receiving an RF signal. The method continues by high pass filtering the RF...
US-6,977,526 Fully differential input buffer with wide signal swing range
A squeezable tail current source for use in a differential operational amplifier is disclosed that regulates the current through a main input differential pair...
US-6,976,187 Rebuilding redundant disk arrays using distributed hot spare space
A method and system that allows the distribution of hot spare space across multiple disk drives that also store the data and redundant data in a fully active...
US-6,976,152 Comparing operands of instructions against a replay scoreboard to detect an instruction replay and copying a...
An apparatus for a processor includes a first scoreboard, a second scoreboard, and a control circuit coupled to the first scoreboard and the second scoreboard....
US-6,976,141 Pipelined multi-access memory apparatus and method
A memory management system provides the ability for multiple requesters to access blocks of memory in a pipelined manner. During a first clock, requests for one...
US-6,975,840 Charge pump for an integrated circuit receiver
A radio transceiver includes a charge pump formed within a local oscillator that adjusts a voltage input to a voltage-controlled oscillator in a manner that...
US-6,975,838 Adaptive radio transceiver with noise suppression
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local...
US-6,975,655 Method of controlling data sampling clocking of asynchronous network nodes in a frame-based communications network
A method of controlling data sampling clocking of asynchronous network nodes, each asynchronous network node having a local clock and transmitting and receiving...
US-6,975,637 Apparatus for ethernet PHY/MAC communication
An integrated Ethernet PHY/MAC apparatus having a single link partner capability register shared between a PHY and a corresponding MAC, which implements IEEE...
US-6,975,557 Phase controlled high speed interfaces
A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased...
US-6,975,324 Video and graphics system with a video transport processor
A video and graphics system includes a data transport processor for receiving compressed data streams, a video transport processor for extracting video data, and...
US-6,975,259 Continuous-time delta-sigma ADC with programmable input range
A scaled input current is produced that substantially matches the full scale input of a CT.DELTA..tau.ADC that substantially cancels an offset bias current...
US-6,975,250 Methods and systems for data manipulation
A method of and device for performing a data expansion operation on a plurality of input data objects to generate expanded output data objects is disclosed. The...
US-6,973,094 Packet-switched multiple-access network system with distributed fair priority queuing
A packet-switched multiple-access network system with a distributed fair priority queuing media access control protocol that provides multiple levels of priority...
US-6,973,058 System and method for accessing a multi-line gateway using cordless telephony terminals
According to the present invention, simultaneous call-handling and data transfer is achieved between a terminal and a multi-line gateway in a cordless telephony...
US-6,972,629 Modulation dependent biasing for efficient and high-linearity power amplifiers
A power amplifier includes a transconductance stage and a modulation detection and bias determination module, and may include a cascode stage. The modulation...
US-6,972,625 Variable transconductance variable gain amplifier utilizing a degenerated differential pair
Continuously tuning a transconductance. Coupling a degeneration resistance from a first source of a first transistor in a differential pair of transistors to a...
US-6,972,616 Low-noise, fast-settling bias circuit and method
A low-noise, fast-settling bias circuit includes a first and a second low pass filter, such as RC filters. The second filter initially shorts out a resistor of...
US-6,972,610 High linearity passive mixer and associated LO buffer
An RF communications system includes a transmit node for transmitting an RF information signal and a receive node for receiving the transmitted RF information...
US-6,972,556 System and method for measuring the power consumed by a circuit on a printed circuit board
A system for measuring power of a circuit on a printed circuit board (PCB) including first and second circuits, a power strip, a power plane, and a calibration...
US-6,971,038 Clock gating of sub-circuits within a processor execution unit responsive to instruction latency counter within...
A processor may include an execution circuit, an issue circuit coupled to the execution circuit, and a clock tree for clocking circuitry in the processor. The...
US-6,971,033 Method and apparatus for improving bus master performance
A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at...
US-6,971,006 Security chip architecture and implementations for cryptography acceleration
An architecture and a method for a cryptography acceleration is disclosed that allows significant performance improvements without the use of external memory....
US-6,970,689 Programmable mixer for reducing local oscillator feedthrough and radio applications thereof
A state of a programmable mixer is set during a calibration phase to minimize local oscillator feedthrough. During a calibration phase, inputs to the...
US-6,970,681 Integrated multimode radio and components thereof
An integrated multimode radio includes a multimode receiver and a multimode transmitter. The multimode receiver includes a shared receiver front-end, a receiver...
US-6,970,434 Hierarchical communication system providing intelligent data, program and processing migration
A hierarchical communication system, arranged in a spanning tree configuration, is described in which wired and wireless communication networks exhibiting...
US-6,970,382 System and method for controlling logical value and integrity of data in memory systems
In a digital memory system, systems and methods that control a logical value and an integrity of data represented by charge are provided. In one embodiment, a...
US-6,968,519 System and method for using IDDQ pattern generation for burn-in tests
A method and system are disclosed for efficiently and effectively toggling logic states of chip elements during a burn-in process of a digital integrated circuit...
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