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Patent # Description
US-6,968,167 Adaptive radio transceiver with calibration
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local...
US-6,968,019 IF FSK receiver
In one embodiment, the present invention is a low-power, and high performance receiver including an IF demodulator for high data rate, frequency modulated...
US-6,967,946 Voice and data exchange over a packet based network with precise tone plan
A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a...
US-6,967,857 Dense content addressable memory cell
A content addressable memory cell (10) comprises a word line 12, a first bit line (14), and a second bit line (16). A pair of transistors (30-31) is arranged to...
US-6,967,529 Large dynamic range programmable gain attenuator
A design of integrated circuit components to prevent accidental turn on when large input signals are accepted. With integrated circuits operated at lower power...
US-6,966,017 Cache memory self test
The benefits of on-chip self testing are widely recognized and include the capability to test at high operating speed and independently of external test...
US-6,965,973 Remote line directory which covers subset of shareable CC-NUMA memory space
A node is coupled to receive a coherency command and coupled to a memory, wherein the node includes a directory configured to track a state of a first number of...
US-6,965,945 System and method for slot based ARL table learning and concurrent table search using range address insertion...
A network device including at least one network port, a clock, address resolution (ARL) tables, and address resolution logic. The at least one network port is...
US-6,965,616 Network data transmission synchronization system and method
A number of features for enhancing the performance of a cable transmission system in which data is transmitted between a cable modem termination system at a...
US-6,965,610 System and method for providing compatibility between different transceivers in a multi-pair communication system
A system and method are disclosed that provide for compatibility between different generations of transceivers, such as Gigabit Ethernet transceivers. According...
US-RE38,876 System for, and method of, processing quadrature amplitude modulated signals
Analog signals encoded with quadrature amplitude modulation (QAM) pass through a coaxial cable at a particular baud rate. These signals have a carrier frequency...
US-6,964,005 System and method for interleaving data in a communication device
A system and method is provided for interleaving data in a communication device. The system includes a memory that stores blocks of data to be interleaved. In...
US-6,963,931 Cable modem system and method for dynamically mixing protocol specific header suppression techniques
A cable modem system and method is provided for the transfer and processing of data in accordance with specialized data transfer protocols while utilizing...
US-6,963,616 Adaptively configurable class-A/class-B transmit DAC to transceiver emission and power consumption control
A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications....
US-6,963,613 Method of communicating between modules in a decoding system
Means of communicating between modules in a decoding system. A variable-length decoding accelerator communicates with a core decoder processor via a co-processor...
US-6,963,346 Method and system for efficiently using fewer blending units for antialiasing
A system and method for providing antialiasing of a graphical image on a display is disclosed. The graphical image is generated from data describing at least one...
US-6,963,288 Apparatus and method for displaying system state information
A programmable LED display system is disclosed. The system includes a programmable controller, a driver operative to generate a control signal in response to a...
US-6,963,251 High noise rejection voltage-controlled ring oscillator architecture
A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring...
US-6,963,248 Phase locked loop
A periodic signal generation circuit includes a differential crystal oscillator suitable for integration on a semiconductor substrate. The oscillator utilizes an...
US-6,963,245 System and method to accelerate settling of an amplifier
A system and method are used to accelerate settling or steady state of an amplifier in an amplifier system. This is used to ensure the amplifier reaches...
US-6,963,221 Methods and circuitry for implementing first-in first-out structure
Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one...
US-6,963,220 Methods and circuitry for implementing first-in first-out structure
Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one...
US-6,963,110 System and method for ESD protection
An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front...
US-6,961,902 Interactive system for and method of automating the generation of legal documents
A method and system for interactively generating legal documents by a requester for a recipient. A legal document server is established on a computer network to...
US-6,961,824 Deterministic setting of replacement policy in a cache
A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a way of the cache. The cache may alter the...
US-6,961,552 LNA gain adjustment for intermodulation interference reduction
The radio receiver includes a low noise amplifier that amplifies a received signal to one of three different gain settings. One gain setting is maximum...
US-6,961,546 Adaptive radio transceiver with offset PLL with subsampling mixers
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local...
US-6,961,372 Non-iterative time-domain equalizer
A method for forming a non-iterative time-domain equalizer (TEQ) and apparatus corresponding thereto. A channel response H(z) is followed by a TEQ response A(z)...
US-6,961,314 Burst receiver for cable modem system
A number of features for enhancing the performance of a cable transmission system in which data is transmitted between a cable modem termination system at a...
US-6,961,312 Hierarchical data collection network supporting packetized voice communications among wireless terminals and...
A packet-based, hierarchical communication system, arranged in a spanning tree configuration, is described in which wired and wireless communication networks...
US-6,960,819 System and method for one-time programmed memory through direct-tunneling oxide breakdown
A one-time programming memory element, capable of being manufactured in a 0.13 .mu.m or below CMOS technology, having a capacitor, or transistor configured as a...
US-6,959,395 Method and apparatus for the conditional enablement of PCI power management
A method and apparatus are disclosed for conditionally enabling/disabling PCI power management in a computer-based system employing a central resource and an...
US-6,959,378 Reconfigurable processing system and method
A reconfigurable processing system executes instructions and configurations in parallel. Initially, a first instruction loads configurations into configuration...
US-6,959,038 High-speed decoder for a multi-pair gigabit transceiver
A method and a system for providing an input signal from a multiple decision feedback equalizer to a decoder based on a tail value and a subset of coefficient...
US-6,958,783 Adaptive non-linear noise reduction techniques
An impulse-reducing module (200) reduces random noise in video pixels by providing an impulse detector (244) and an impulse reducer, such as a median filter...
US-6,958,654 Layout technique for matched resistors on an integrated circuit substrate
Provided a method of reducing impedance variations in an electrical circuit structured and arranged for placement on an integrated circuit (IC) substrate. The...
US-6,958,648 Programmable gain amplifier with glitch minimization
A programable gain amplifier (PGA) has an amplifier and a variable resistor that is connected to the output of the amplifier. The variable resistor includes a...
US-6,957,306 System and method for controlling prefetching
Systems and methods that control prefetching are provided. In one embodiment, a system may include, for example, a prefetch buffer system coupled to a processing...
US-6,957,290 Fast arbitration scheme for a bus
A distributed arbitration scheme includes arbiters with each agent. The arbiters receive request signals indicating which agents are arbitrating for the bus....
US-6,956,621 High impedance digital full line video clamp
A circuit for clamping a TV signal includes an input capacitor coupled to the TV signal, an analog-to-digital converter that outputs a digital signal...
US-6,956,513 Error feedback structure for delta-sigma modulators with improved stability
An error feedback circuit includes a first summer receiving an analog input signal and a feedback signal and outputting a summed signal. A quantizer receives the...
US-6,956,436 Wide common mode differential input amplifier and method
A wide input range amplifier includes a first and second stage. The first stage has first and second inputs, first and second outputs, and first, second and...
US-6,956,434 MOSFET well biasing scheme that mitigates body effect
A biasing scheme for a MOSFET that mitigates the MOSFET body effect. The biasing scheme can be realized replicating the voltage at the source terminal of a...
US-6,956,414 System and method for creating a limited duration clock divider reset
Systems and methods for creating a limited duration clock divider reset are disclosed. Aspects of the invention may include a method for resetting a chip or a...
US-6,954,832 Interleaver for iterative decoder
Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is...
US-6,954,800 Method of enhancing network transmission on a priority-enabled frame-based communications network
A method of enhancing network transmission between stations on a priority-enabled frame-based communications network, the communications network having multiple...
US-6,954,708 System and method for detecting a device requiring power
A system and technique for detecting a device that requires power is implemented with a power detection station. The power detection system includes a detector...
US-6,954,490 Fully integrated ethernet transmitter architecture with interpolating filtering
A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications....
US-6,954,162 Low power, high SNR, high order delta sigma modulator stage having integrators with pipelined cross coupled...
In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator...
US-6,954,114 NCO with rational frequency and normalized phase
A numerically controlled oscillator (NCO) system for generating rational frequencies with normalized phase is disclosed. In one embodiment, the system comprises...
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