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Patent # Description
US-6,954,114 NCO with rational frequency and normalized phase
A numerically controlled oscillator (NCO) system for generating rational frequencies with normalized phase is disclosed. In one embodiment, the system comprises...
US-6,952,791 Method and circuit for initializing a de-skewing buffer in a clock forwarded system
A method and circuit for initializing a buffer in a clock forwarded system. A buffer is configured for temporarily storing incoming data received on the...
US-6,952,401 Method for load balancing in a network switch
A method for load balancing in a link aggregation environment, wherein the method includes the steps of determining if a packet flow in a network switch exceeds...
US-6,952,137 System and method for automatic parameter adjustment within a phase locked loop system
A signal recovery system and methods to quickly acquire signal lock and maintain consistent performance of the signal recovery system for different signal input...
US-6,952,136 System to reduce unwanted oscillations in high speed, high gain or transimpedance amplifiers
A system reduces unwanted oscillations in a multiple gigabit per second, high gain amplifier portion. The system includes a power source portion having a...
US-6,952,134 Protection circuit for extending headroom with off-chip inductors
A protection circuit for extending the dynamic range of an amplifier circuit is described. Off-chip impedances, such as inductors, cause the output of the...
US-6,952,053 Metal bond pad for integrated circuits allowing improved probing ability of small pads
The present invention is a metal bond pad that provides electrical and mechanical connection to an integrated circuit (IC). The metal bond pad is configured to...
US-6,950,973 Dynamic scan circuitry for A-phase
A first dynamic logic circuit has an output node on which a scan value is provided during scan, a second dynamic logic circuit, and one or more third dynamic...
US-6,950,430 Switch fabric with path redundancy
A method of forwarding data in a network switch fabric is disclosed. An incoming data packet is received at a first port of the fabric and a first packet...
US-6,950,355 System and method to screen defect related reliability failures in CMOS SRAMS
A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of...
US-6,950,049 Computer program product for performing digital-to-analog conversion
The present invention is directed to a sigma-delta digital to analog converted (DAC) including a digital-sigma delta modulator, a decimation filter, and a...
US-6,949,988 Constant impedance filter
A constant impedance filter maintains a constant input impedance for frequencies that are both inside the filter passband and outside the filter passband. The...
US-6,949,964 Sub-micron high input voltage tolerant input output (I/O) circuit
A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the...
US-6,949,910 Methods and systems for battery charging control based on CMOS technology
A method and system, compatible with low-voltage CMOS technology, for controlling the charging of a battery. The method includes monitoring a battery voltage...
US-6,948,035 Data pend mechanism
A node comprises an interconnect, circuitry coupled to the interconnect and configured to initiate a transaction on the interconnect, and a control circuit...
US-6,947,715 VOFDM receiver correlation matrix processing using factorization
Vector orthogonal frequency division multiplexing (VOFDM) receiver correlation matrix processing using factorization. Efficient correlation matrix processing is...
US-6,947,482 System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system
A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage...
US-6,947,350 Synchronous controlled, self-timed local SRAM block
The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local...
US-6,947,010 Eccentric spiral antenna
A system includes a support device and an elongated spiral antenna coupled to the support device. The elongated spiral antenna has a contracted portion and an...
US-6,946,896 High temperature coefficient MOS bias generation circuit
A high temperature coefficient includes a temperature dependent bias generation circuit serially coupled with a variable resistance. The resistance of the...
US-6,944,746 RISC processor supporting one or more uninterruptible co-processors
A system and method for processing instructions in a computer system comprising a processor and a co-processor communicatively coupled to the processor....
US-6,944,719 Scalable cache coherent distributed shared memory processing system
A packetized I/O link such as the HyperTransport protocol is adapted to transport memory coherency transactions over the link to support cache coherency in...
US-6,944,435 Unconditionally stable on-chip filter and applications thereof
An unconditionally stable on-chip filter includes a filtering section and at least one negative resistance module. The filtering section is operably coupled to...
US-6,944,250 Variable rate modulator
Digital data signals at a variable input frequency are converted by a numerically controlled oscillator and an interpolator to a signal at a fixed output...
US-6,944,249 Method and system for transmitting isochronous voice in a wireless network
In one aspect the present invention describes an electronic circuit for transmitting voice packet data over a wireless network with an upstream transmission mode...
US-6,944,237 Multi-pair transceiver decoder system with low computation slicer
A method and a system for decoding information signals encoded by a multi-state encoding architecture and transmitted over a multi-dimensional transmission...
US-6,943,718 System and method to substantially eliminate glitch in a digital to analog converter
A system (e.g., a digital-to-analog converter (DAC)) includes a digital section and an analog section. The digital section has drivers that generate drive...
US-6,943,622 Input buffer amplifier with centroidal layout
An input buffer amplifier has a symmetrical centroidal layout. The input buffer amplifier includes two half differential amplifiers that have substantially...
US-6,943,596 Power-on reset circuit for use in low power supply voltage applications
Systems and methods are disclosed for a power-on reset used in low power supply voltage applications (i.e., having a full operating power supply voltage of less...
US-6,943,589 Combination multiplexer and tristate driver circuit
A combination multiplexer and tristate circuit. A multiplexer circuit may be configured to receive at least a first data input and a second data input, which are...
US-6,943,587 Switchable power domains for 1.2V and 3.3V pad voltages
An integrated circuit includes a core circuit and a buffer circuit. The buffer circuit includes a plurality of input buffers and a plurality of output buffers...
US-6,941,440 Addressing scheme supporting variable local addressing and variable global addressing
A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on...
US-6,941,406 System having interfaces and switch that separates coherent and packet traffic
An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory...
US-6,941,334 Higher precision divide and square root approximations
A floating point unit includes a multiplier, an approximation circuit, and a control circuit coupled to the multiplier and the approximation circuit. The...
US-6,941,116 Linearization technique for phase locked loops employing differential charge pump circuitry
A differential linear fractional N-synthesizer includes a phase and frequency detection module, a linearized charge pump, a low pass filter, a voltage controlled...
US-6,940,929 Low-latency high-speed trellis decoder
A method for decoding a word received at a current time instant into a symbol of a trellis code. The trellis code corresponds to a trellis diagram having N...
US-6,940,928 Method and apparatus for soft-in soft-out turbo code decoder
Method and apparatus for Soft In Soft Out Turbo Code Decoder. Metrics are received by a decoder having SISO unit(s). The SISO unit computes all the alpha values...
US-6,940,904 Artifact-free displaying of MPEG-2 video in the progressive-refresh mode
A method and apparatus for decoding and displaying a progressive refresh bitstream, such as, for example, Motorola/GI HITS bitstream, is provided. The method...
US-6,940,766 Row-column repair technique for semiconductor memory arrays
A method for locating a repair solution for a memory that includes a memory array comprising a plurality of rows and a plurality of columns, N redundant rows,...
US-6,940,560 Method and system for performing PAL luma two line vertical combing
A method and system for performing combing for PAL luma data is disclosed. The combing is performed for a display having a plurality of lines. The display is...
US-6,940,434 Methods and systems for digital dither
Methods and systems for applying digital dither includes methods and systems for applying digital dither in data converters, such as, for example, delta-sigma...
US-6,940,334 Methods and systems for generating interim voltage supplies
Methods and systems for protecting integrated circuits ("ICs") from power-on sequencing problems provide an interim voltage during power-on sequences in order to...
US-6,940,306 Methods and circuitry for implementing first-in first-out structure
Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one...
US-6,940,293 Modeling miller effect in static timing analysis
A method is contemplated. According to the method, capacitances in a first resistance/capacitance (RC) extraction corresponding to a circuit are modified. Each...
US-6,938,229 Method and apparatus for analyzing post-layout timing violations
A tool for analyzing timing violations reports is presented herein. The tool comprises a script which parses a log file containing any number of timing violation...
US-6,937,538 Asynchronously resettable decoder for a semiconductor memory
A hierarchical memory structure having memory cells, and sense amplifiers and decoders coupled with the memory cells to form first tier memory module, and...
US-6,937,251 Method and system for improving color quality of three-dimensional rendered images
A method and system for providing a graphical image on a display is disclosed. The image is provided from data describing at least one object. The display...
US-6,937,177 Shuffler apparatus and related dynamic element matching technique for linearization of unit-element...
A data shuffler apparatus shuffles input bits to perform dynamic element matching. The shuffler apparatus includes N input shufflers, each input shuffler having...
US-6,937,128 On-chip inductor having a square geometry and high Q factor and method of manufacture thereof
An on-chip inductor and/or on-chip transformer includes at least one dielectric layer and at least one conductive winding on the at least one dielectric layer....
US-6,937,080 Current-controlled CMOS logic family
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3 MOS) logic fabricated in conventional CMOS process...
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