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Patent # Description
US-6,934,937 Multi-channel, multi-service debug on a pipelined CPU architecture
A method and system for debugging an executing service on a pipelined CPU architecture are described. In one embodiment, a breakpoint within an executing service...
US-6,934,866 Network interface using programmable delay and frequency doubler
A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an...
US-6,934,787 Adaptable switch architecture that is independent of media types
A network device for handling data and a method for handling data in a network device are disclosed. The network device includes at least one media port and at...
US-6,934,176 Systems for programmable memory using silicided poly-silicon fuses
The present invention is directed to systems for evaluating one-time programmable memory cells. A threshold current is applied to a resistive circuit, thereby...
US-6,933,870 Method and apparatus for efficient mixed signal processing in a digital amplifier
A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate...
US-6,933,778 Method and apparatus for efficient mixed signal processing in a digital amplifier
A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate...
US-6,933,547 Memory cell for modification of default register values in an integrated circuit chip
A memory cell circuit for modification of a default register value in an integrated circuit chip, which includes a plurality of metal layers and first and second...
US-6,931,494 System and method for directional prefetching
Systems and methods that provide directional prefetching are provided. In one embodiment, a method may include one or more of the following: storing a first...
US-6,931,267 Bias filtering module including MOS capacitors
A bias filtering module with at least two capacitive levels satisfies both a settle time requirement and a filtering requirement using a voltage dependent filter...
US-6,931,079 Power reduction
There is disclosed a technique in which any peaks above a threshold level are reduced, but not clipped, such that the effects of such peaks is reduced. Although...
US-6,931,073 Reduction of aggregate EMI emissions of multiple transmitters
A power efficient and reduced electromagnetic interference (EMI) emissions multi-transmitter system for unshielded twisted pair (UTP) data communication...
US-6,930,677 Method and system for performing PAL chroma two-line vertical combing
A method and system for performing combing for PAL chroma data for a display having a plurality of lines is disclosed. The display is capable of depicting a...
US-6,930,626 Computer program product for mismatched shaping of an oversampled converter
Methods and apparatuses for spectrally shaping mismatch errors in a multi-bit digital to analog converter (DAC). In an embodiment, the multi-bit DAC is...
US-6,930,621 Method to overlay a secondary communication channel onto an encoded primary communication channel
Disclosed herein is a method and system for providing a secondary communication channel overlaid on a primary communication channel using an enhanced encoding...
US-6,930,545 Switched-capacitor, common-mode feedback circuit for a differential amplifier without tail current
Provided is a switched capacitor feedback circuit including two or more input ports configured to receive a corresponding a number of input signals and at least...
US-6,930,528 Delay circuit and method with delay relatively independent of process, voltage, and temperature variations
Methods and systems for controlling delay relatively independent of process, supply-voltage, and/or temperature ("PVT") variations include sensing an output...
US-6,930,519 Frequency division/multiplication with jitter minimization
A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency...
US-6,930,512 One-level zero-current-state exclusive or (XOR) gate
Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured...
US-6,928,588 System and method of improving memory yield in frame buffer memory using failing memory location
A method is provided for testing buffer memory. The method includes a step of testing a buffer memory having a plurality of memory locations including redundant...
US-6,928,573 Communication clocking conversion techniques
A plurality of groups of first flip-flops (group 40 of flip-flops A1-An-1 for each of channels CIA-CIC) store input data clocked in response to first clock...
US-6,928,559 Battery powered device with dynamic power and performance management
A computing device operates over a range of voltages and frequencies and over a range of processor usage levels. The computing device includes at least a...
US-6,928,495 Method and system for an adaptive multimode media queue
Embodiments of the invention may provide a method for implementing an adaptive multimode media queue. A mode of operation may be determined for a received media...
US-6,928,302 Radio card having independent antenna interface supporting antenna diversity
A radio card, such as a PCMCIA card, received by an electronic device has a first interface coupling radio circuitry within the radio card to the electronic...
US-6,928,295 Wireless device authentication at mutual reduced transmit power
A system and method for facilitating the authentication of wireless devices in an environment with multiple wireless networks. A user wishing to join an...
US-6,928,109 Method and apparatus for converting between byte lengths and burdened burst lengths in a broadband...
Requests are processed to transmit data packets upstream from a cable modem to a cable headend in a manner that minimizes the use of CPU operations and/or memory...
US-6,928,106 Phy control module for a multi-pair gigabit transceiver
A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY...
US-6,928,026 Synchronous global controller for enhanced pipelining
The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and...
US-6,928,018 Dynamic register with low clock rate testing capability
A method for refreshing data in a circuit element included in a dynamic register. A static loop is coupled to the circuit element as a feedback path from the...
US-6,927,783 Graphics display system with anti-aliased text and graphics feature
A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video...
US-6,927,640 Apparatus and method for reducing phase noise in oscillator circuits
A resonant oscillator circuit includes an active device and a resonator that causes the active device to oscillate at a resonant frequency of the resonator. The...
US-6,927,631 Wideband CMOS gain stage
A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is...
US-6,927,606 Low voltage differential to single-ended converter
Method and circuitry for converting a differential logic signal to a single-ended logic signal eliminate slower PMOS transistors and speed up the conversion...
US-6,927,565 Dynamic register with IDDQ testing capability
The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating...
US-6,925,590 Scan interface
A scan interface for an integrated circuit includes a scan clock and a scan mode signal. The scan mode signal is indicative of whether or not scan is active, and...
US-6,925,174 Interaction between echo canceller and packet voice processing
System and method for processing communication signals in a communication system having a detector for detecting a parameter of a communication signal. A...
US-6,925,130 Method and system for a reduced emissions direct drive transmitter for unshielded twisted pair (UTP) applications
A reduced emission transmitter may include an encoder block, which may be partitioned into a first group comprising odd encoder processing cells and a second...
US-6,924,712 Semi-suspended coplanar waveguide on a printed circuit board
A printed circuit board includes two differential signal traces, a layer of core material, a layer of filler material, and a ground plane. The filler material is...
US-6,922,739 System and method for dual IDE channel servicing using single multiplexed interface having first and second...
An integrated receiver with dual channel transport stream decoding and delivery substantially implemented on a single CMOS integrated circuit is described. For...
US-6,922,397 Selectable training signals based on stored previous connection information for DMT-based system
Training signals can be chosen based on stored prior connection information to reduce the use of extra tones in transmitted training signals and thereby improve...
US-6,922,109 Multiple synthesized clocks with fractional PPM control from a single clock source
A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input...
US-6,920,592 System, method, and apparatus for detecting and recovering from false synchronization
Presented herein are a system(s), method(s), and apparatus for detecting and recovering from false synchronization. False synchronization can be detected on the...
US-6,920,552 Network interface with double data rate and delay locked loop
A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The...
US-6,920,520 Methods and circuits for stacking bus architecture
A system for connecting multiple repeaters into a single collision domain comprising a first repeater, a second repeater and a stacking bus. The first repeater...
US-6,920,311 Adaptive radio transceiver with floating MOSFET capacitors
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local...
US-6,919,858 RF antenna coupling structure
An RF antenna coupling structure includes a first transformer, a second transformer, and a transformer balun. The first transformer includes a primary winding...
US-6,919,832 Methods and systems for high speed quantizers
Methods and systems for improved feedback processing in delta-sigma modulators, including single bit and multi-bit delta-sigma modulators, continuous-time and...
US-6,918,031 Setting condition values in a computer
A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described....
US-6,918,029 Method and system for executing conditional instructions using a test register address that points to a test...
A method and system of executing computer instructions is described. Each instruction defines first and second operands and an operation to be carried out on...
US-6,918,008 Internal evict with external request
A cache is configured to select a cache block for eviction in response to detecting a cache miss. The cache transmits the address of the cache block as a write...
US-6,917,789 Adaptive radio transceiver with an antenna matching circuit
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local...
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