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Self-repairing built-in self test for linked list memories
A process of repairing defects in linked list memories including selecting one of a group of the linked list memories and an additional memory, as a defect...
Analog to digital converter that services voice communications
An Analog-to-Digital-Converter (ADC) converts an analog signal to digital data. The ADC includes a modulator, a decimation filter, and a time dither clock...
NCO based timebase recovery system and method for A/V decoder
Systems and methods are disclosed for recovering a clock or time reference for A/V systems. One method comprises receiving at least one input time reference...
Optimization of routing layers and board space requirements for ball grid
array package implementations...
A method and apparatus for improved contact pad arrays and land patterns for integrated circuit packages are presented. A plurality of conductive pads are...
System and method for hardware based reassembly of a fragmented packet
A system and method for hardware based reassembly of a fragmented packet is shown. The method includes receiving a bandwidth request to transfer a data packet...
Direct tuning of embedded integrated circuit components
A method and apparatus for direct tuning of a component embedded within an integrated circuit includes processing that begins by providing a plurality of...
Method and apparatus to identify a remote communication apparatus and
enhance communication performance based...
A type or brand of remote communication device is identified by measuring one or more characteristics associated with one or more signals sent by the remote...
High bandwidth, high PSRR, low dropout voltage regulator
A voltage regulator may include one or more features for generating high PSRR. For example, source follower devices may be included in the voltage regulator for...
Input circuit with hysteresis
An input circuit has hysteresis to mitigate the effects of input noise. The input circuit receives an analog input signal and determines whether the unregulated...
Clock multiplier using masked control of clock pulses
A clock multiplier circuit receives a clock input signal and generates a clock output signal. The clock multiplier circuit generates a number of pulses to be...
Sub-micron high input voltage tolerant input output (I/O) circuit
A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the...
Filter calibration and applications thereof
A method for calibrating a filter begins with the filter filtering a first signal having a first frequency to produce a first filtered signal, wherein the first...
Apparatus and method for managing memory in a network switch
The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory,...
System having two or more packet interfaces, a switch, and a shared packet
An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA...
System and method of processing data flow in multi-channel, multi-service
environment by dynamically allocating...
A method and system for processing a data flow in a multi-channel, multi-service environment is described. In one embodiment, a socket is dynamically allocated,...
Voice gateway with echo cancellation
A network gateway is configured to facilitate on line and off line bi-directional communication between a number of near end data and telephony devices with far...
Method and system for fast memory access
An address device simultaneously provides a first address to a first memory section using a first address bus and a second, incrementally higher, address to a...
Method to overlay a secondary communication channel onto an encoded primary
The disclosure relates to providing a secondary communication channel overlaid on a primary communication channel, using an enhanced encoding method, to...
Method and system for producing a drive signal for a current steering
Provided is a method and system for producing a drive signal for a current steering amplifier. An exemplary method comprises receiving a supply voltage signal...
Current-controlled CMOS circuit using higher voltage supply in low voltage
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3 MOS) logic fabricated in conventional CMOS process...
Data processing and communications device with interchangeable modules
A data communications device includes a base unit having a first microprocessor and a data and communication module received by the base unit that includes a...
Linear full-rate phase detector and clock and data recovery circuit
Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate...
Phase-locked loop circuit
Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device...
Method and apparatus for the reduction of upstream request processing
latency in a cable modem termination system
Upstream requests such a bandwidth requests, are processed by CMTS out of order on a priority basis to reduce latency in responding to the request. Specifically,...
System for and method of providing a header and a trailer in data packets
Each packet normally consists of a preamble, start-of-frame delimiter and data. The preamble has nibbles each having a particular format. A header substituted...
Burn in system and method for improved memory reliability
A system and method for applying a stress to a hierarchical memory structure in parallel, testing the memory structure for weak defects. The system and method...
Dense content addressable memory cell
A content addressable memory cell (10) comprises a word line 12, a first bit line (14), and a second bit line (16). A pair of transistors (30-31) is arranged to...
System and method for tuning output drivers using voltage controlled
oscillator capacitor settings
The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such...
Current-controlled CMOS circuits with inductive broadbanding
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3 MOS) logic with inductive broadbanding fabricated in...
Per CoS memory partitioning
A network device for monitoring a memory partitioned by an identifier can include at least one port configured to receive at least one packet. The at least one...
A magnitude comparator circuit may include a first circuit coupled to receive the operands to be compared, a second circuit coupled to the first circuit, and a...
On-chip impedance matching power amplifier and radio applications thereof
An on-chip impedance matching includes a transistor, an inductor, and a capacitive divider. The gate of the transistor is operably coupled to receive input...
Digital demodulation and applications thereof
A digital demodulator that may be utilized in integrated radio receivers and/or integrated radios includes a mixing section, 1.sup.st and 2.sup.nd digital comb...
Frequency diverse single carrier modulation for robust communication over
The present invention provides a frequency-diverse single-carrier modulation scheme that extends the usable SNR range of severely distorted channels. This scheme...
PRBS generator selection in modem communication
The present invention relates to a system and method for selecting one of plurality of PRBS generators for use with a modem. The modem includes a measuring...
Network switch enhancements directed to processing of internal operations
in the network switch
A method of processing internal operations in a network switch includes the steps of constructing a lookup table in system memory by snooping a communication...
Compact and highly efficient DRAM cell
A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing,...
Method and system for providing edge antialiasing
A system and method for generating a graphical image on a display is disclosed. The graphical image is generated from data describing at least one object. The...
Apparatus for generating a magnetic interface and applications of the same
A magnetic interface generator generates a magnetic interface at a center frequency f.sub.0. The magnetic interface generator is a passive array of spirals that...
Apparatus and method for delay matching of full and divided clock signals
A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference...
System and method utilizing a one-stage level shift circuit
A system and method for level shifting a core, lower voltage in a one-stage level shift device to produce a higher, driving voltage. The system includes a first...
Transceiver having shadow memory facilitating on-transceiver collection and
communication of local parameters
The present invention relates to a register for a single chip multi-sublayer PHY. More specifically, the present invention relates to a transceiver module...
Ball grid array package with patterned stiffener layer
Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. An IC die is mounted in a centrally located cavity of a...
Method and apparatus for coupling a voiceband modem circuit to a common
A method and apparatus for coupling a voiceband modem circuit to a common phoneline connector, the common phoneline connection having a ring line connection and...
DSL rate adaptation
A method for enhancing the bit rate and/or margin at which quadrature amplitude modulation (QAM) communication is performed includes the steps of varying a...
Very small swing high performance CMOS static memory (multi-port register
file) with power reducing column...
The present invention relates to storage element. At least one read port is coupled to the storage element and a sensing device is coupled to the read port,...
Memory cell with fuse element
The present invention relates to a programmable memory device and a method of setting a state for a programmable memory device. In at least one embodiment, the...
Content addressable memory cell techniques
A content addressable memory cell (10) includes a circuit (20) operating from a predetermined supply voltage (VDD) for storing a first bit of data at a first...
Slew rate controlled output buffer
An output buffer includes first and second circuit portions coupled between input and output terminals. Each circuit portion includes a capacitive element; an...
High-density metal capacitor using dual-damascene copper interconnect
An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process,...