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Patent # Description
US-6,917,548 Self-repairing built-in self test for linked list memories
A process of repairing defects in linked list memories including selecting one of a group of the linked list memories and an additional memory, as a defect...
US-6,917,318 Analog to digital converter that services voice communications
An Analog-to-Digital-Converter (ADC) converts an analog signal to digital data. The ADC includes a modulator, a decimation filter, and a time dither clock...
US-6,917,247 NCO based timebase recovery system and method for A/V decoder
Systems and methods are disclosed for recovering a clock or time reference for A/V systems. One method comprises receiving at least one input time reference...
US-6,916,995 Optimization of routing layers and board space requirements for ball grid array package implementations...
A method and apparatus for improved contact pad arrays and land patterns for integrated circuit packages are presented. A plurality of conductive pads are...
US-6,915,358 System and method for hardware based reassembly of a fragmented packet
A system and method for hardware based reassembly of a fragmented packet is shown. The method includes receiving a bandwidth request to transfer a data packet...
US-6,915,114 Direct tuning of embedded integrated circuit components
A method and apparatus for direct tuning of a component embedded within an integrated circuit includes processing that begins by providing a plurality of...
US-6,914,933 Method and apparatus to identify a remote communication apparatus and enhance communication performance based...
A type or brand of remote communication device is identified by measuring one or more characteristics associated with one or more signals sent by the remote...
US-6,914,476 High bandwidth, high PSRR, low dropout voltage regulator
A voltage regulator may include one or more features for generating high PSRR. For example, source follower devices may be included in the voltage regulator for...
US-6,914,466 Input circuit with hysteresis
An input circuit has hysteresis to mitigate the effects of input noise. The input circuit receives an analog input signal and determines whether the unregulated...
US-6,914,459 Clock multiplier using masked control of clock pulses
A clock multiplier circuit receives a clock input signal and generates a clock output signal. The clock multiplier circuit generates a number of pulses to be...
US-6,914,456 Sub-micron high input voltage tolerant input output (I/O) circuit
A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the...
US-6,914,437 Filter calibration and applications thereof
A method for calibrating a filter begins with the filter filtering a first signal having a first frequency to produce a first filtered signal, wherein the first...
US-6,912,637 Apparatus and method for managing memory in a network switch
The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory,...
US-6,912,602 System having two or more packet interfaces, a switch, and a shared packet DMA circuit
An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA...
US-6,912,576 System and method of processing data flow in multi-channel, multi-service environment by dynamically allocating...
A method and system for processing a data flow in a multi-channel, multi-service environment is described. In one embodiment, a socket is dynamically allocated,...
US-6,912,209 Voice gateway with echo cancellation
A network gateway is configured to facilitate on line and off line bi-directional communication between a number of near end data and telephony devices with far...
US-6,912,173 Method and system for fast memory access
An address device simultaneously provides a first address to a first memory section using a first address bus and a second, incrementally higher, address to a...
US-6,911,922 Method to overlay a secondary communication channel onto an encoded primary communication channel
The disclosure relates to providing a secondary communication channel overlaid on a primary communication channel, using an enhanced encoding method, to...
US-6,911,865 Method and system for producing a drive signal for a current steering amplifier
Provided is a method and system for producing a drive signal for a current steering amplifier. An exemplary method comprises receiving a supply voltage signal...
US-6,911,855 Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3 MOS) logic fabricated in conventional CMOS process...
US-6,910,632 Data processing and communications device with interchangeable modules
A data communications device includes a base unit having a first microprocessor and a data and communication module received by the base unit that includes a...
US-6,909,852 Linear full-rate phase detector and clock and data recovery circuit
Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate...
US-6,909,762 Phase-locked loop circuit
Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device...
US-6,909,715 Method and apparatus for the reduction of upstream request processing latency in a cable modem termination system
Upstream requests such a bandwidth requests, are processed by CMTS out of order on a priority basis to reduce latency in responding to the request. Specifically,...
US-6,909,712 System for and method of providing a header and a trailer in data packets
Each packet normally consists of a preamble, start-of-frame delimiter and data. The preamble has nibbles each having a particular format. A header substituted...
US-6,909,648 Burn in system and method for improved memory reliability
A system and method for applying a stress to a hierarchical memory structure in parallel, testing the memory structure for weak defects. The system and method...
US-6,909,623 Dense content addressable memory cell
A content addressable memory cell (10) comprises a word line 12, a first bit line (14), and a second bit line (16). A pair of transistors (30-31) is arranged to...
US-6,909,332 System and method for tuning output drivers using voltage controlled oscillator capacitor settings
The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such...
US-6,909,309 Current-controlled CMOS circuits with inductive broadbanding
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3 MOS) logic with inductive broadbanding fabricated in...
US-6,907,453 Per CoS memory partitioning
A network device for monitoring a memory partitioned by an identifier can include at least one port configured to receive at least one packet. The at least one...
US-6,907,443 Magnitude comparator
A magnitude comparator circuit may include a first circuit coupled to receive the operands to be compared, a second circuit coupled to the first circuit, and a...
US-6,907,231 On-chip impedance matching power amplifier and radio applications thereof
An on-chip impedance matching includes a transistor, an inductor, and a capacitive divider. The gate of the transistor is operably coupled to receive input...
US-6,907,089 Digital demodulation and applications thereof
A digital demodulator that may be utilized in integrated radio receivers and/or integrated radios includes a mixing section, 1.sup.st and 2.sup.nd digital comb...
US-6,907,086 Frequency diverse single carrier modulation for robust communication over in-premises wiring
The present invention provides a frequency-diverse single-carrier modulation scheme that extends the usable SNR range of severely distorted channels. This scheme...
US-6,907,062 PRBS generator selection in modem communication
The present invention relates to a system and method for selecting one of plurality of PRBS generators for use with a modem. The modem includes a measuring...
US-6,907,036 Network switch enhancements directed to processing of internal operations in the network switch
A method of processing internal operations in a network switch includes the steps of constructing a lookup table in system memory by snooping a communication...
US-6,906,946 Compact and highly efficient DRAM cell
A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing,...
US-6,906,728 Method and system for providing edge antialiasing
A system and method for generating a graphical image on a display is disclosed. The graphical image is generated from data describing at least one object. The...
US-6,906,682 Apparatus for generating a magnetic interface and applications of the same
A magnetic interface generator generates a magnetic interface at a center frequency f.sub.0. The magnetic interface generator is a passive array of spirals that...
US-6,906,564 Apparatus and method for delay matching of full and divided clock signals
A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference...
US-6,906,552 System and method utilizing a one-stage level shift circuit
A system and method for level shifting a core, lower voltage in a one-stage level shift device to produce a higher, driving voltage. The system includes a first...
US-6,906,426 Transceiver having shadow memory facilitating on-transceiver collection and communication of local parameters
The present invention relates to a register for a single chip multi-sublayer PHY. More specifically, the present invention relates to a transceiver module...
US-6,906,414 Ball grid array package with patterned stiffener layer
Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. An IC die is mounted in a centrally located cavity of a...
US-6,904,133 Method and apparatus for coupling a voiceband modem circuit to a common phoneline connector
A method and apparatus for coupling a voiceband modem circuit to a common phoneline connector, the common phoneline connection having a ring line connection and...
US-6,904,082 DSL rate adaptation
A method for enhancing the bit rate and/or margin at which quadrature amplitude modulation (QAM) communication is performed includes the steps of varying a...
US-6,903,996 Very small swing high performance CMOS static memory (multi-port register file) with power reducing column...
The present invention relates to storage element. At least one read port is coupled to the storage element and a sensing device is coupled to the read port,...
US-6,903,993 Memory cell with fuse element
The present invention relates to a programmable memory device and a method of setting a state for a programmable memory device. In at least one embodiment, the...
US-6,903,952 Content addressable memory cell techniques
A content addressable memory cell (10) includes a circuit (20) operating from a predetermined supply voltage (VDD) for storing a first bit of data at a first...
US-6,903,588 Slew rate controlled output buffer
An output buffer includes first and second circuit portions coupled between input and output terminals. Each circuit portion includes a capacitive element; an...
US-6,902,972 High-density metal capacitor using dual-damascene copper interconnect
An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process,...
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