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Method for cancelling conditional delay slot instructions
A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot...
Translational loop transmitter architecture employing channel power ratio
measurements for modulation accuracy...
A Radio Frequency RF transmitter includes a translational loop architecture that supports non-constant envelope modulation types and includes by adjusting the...
Packet based network exchange with rate synchronization
A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a...
Method for selecting frame encoding parameters to improve transmission
performance in a frame-based...
A method for selecting frame encoding parameters to improve transmission performance for a transmitting frame being transmitted from a transmitting station to a...
Synchronous controlled, self-timed local SRAM block
The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local...
Method and system for efficiently loading primitives into processors of a
A method and system for more efficiently loading a plurality of primitives for a scene into processors of a computer graphics system is disclosed. Each primitive...
On-chip transformer balun
A transformer balun is obtained that is symmetrical in structure, provides high current, or high voltage, amplification and has high coupling coefficients while...
Highly stable integrated time reference
An integrated oscillator that may be used as a time clock includes circuitry that oscillates about an RC time constant, which RC time constant is adjustable to...
Radio frequency integrated circuit having an antenna diversity structure
A radio frequency integrated circuit includes a power amplifier, a low noise amplifier, a first transformer balun, and a second transformer balun. The power...
Transimpedance amplifier and offset correction mechanism and method for
A system for receiving signals (e.g., optical signals) includes an input device, an amplification device, and a feedback device. The amplification device...
Apparatus for frequency dividing a master clock signal by a non-integer
A frequency dividing circuit divides a master clock frequency by a non-integer factor to provide an output clock signal whose frequency is equal to the frequency...
Programmable divider with built-in programmable delay chain for
high-speed/low power application
A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock...
Thermally and electrically enhanced ball grid array packaging
Electrically and thermally enhanced die-up ball grid array (BGA) packages are described. A BGA package includes a stiffener, substrate, a silicon die, and solder...
Continuous time .DELTA..SIGMA. ADC with dithering
The present invention employs a mixture of digital signal processing and analog circuitry to reduce spurious noise in continuous time delta sigma ...
Integrated switchless programmable attenuator and low noise amplifier
An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front...
Method, apparatus and system for high-speed transmission on fiber optic
Multi-carrier modulation fiber optic systems constructed using a series of electrical carriers, modulating the data on the electrical carriers and combining the...
Address resolution snoop support for CPU
A method of constructing a lookup table for network switch includes the steps of snooping a communication channel in the network switch for lookup table...
Graphics display system with anti-flutter filtering and vertical scaling
A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video...
System and method for compensating for supply voltage induced clock delay
Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog...
Power management unit for use in portable applications
A voltage regulator includes a first stage capable of receiving a reference voltage and capable of having a first current flowing through the first stage. A...
Ball grid array package substrates and method of making the same
An electrically and mechanically enhanced die-down tape substrate ball grid array (BGA) package substrate is described. An IC package includes a substrate that...
Seal ring for integrated circuits
The present invention is directed to a seal structure and a method for forming a seal structure for a semiconductor die. An elongate region which is electrically...
Technique to assess timing delay by use of layout quality analyzer
In one embodiment, a computer readable medium comprises at least first instructions and second instructions. The first instructions, when executed, compute a...
Mechanism for processing speclative LL and SC instructions in a pipelined
A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one...
Memory controller with programmable configuration
A memory controller provides programmable flexibility, via one or more configuration registers, for the configuration of the memory. The memory may be optimized...
Method for distributing sets of collision resolution parameters in a
frame-based communications network
A method for distributing sets of collision resolution parameters to be used for resolution of network access contention events among nodes of a non-centralized...
Switch assisted frame aliasing for storage virtualization
An apparatus and process for relabelling and redirecting at least some of the read transaction data frames and the write transaction write data and transfer...
Fast flexible filter processor based architecture for a network device
A method of filtering data packets in a network device is disclosed. An incoming packet is received from a port and the incoming packet is inspected and packet...
Enhanced die-up ball grid array package with two substrates
An electrically and thermally enhanced die-up ball grid array (BGA) package is described. An integrated circuit (IC) package includes a first substrate, a second...
Method for increasing rate at which a comparator in a metastable condition
transitions to a steady state
A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in...
High linearity large bandwidth, switch insensitive, programmable gain
An apparatus for providing a programmable gain attenuator (PGA) while minimizing the influence of semiconductor switches on the signal being attenuated. An...
Selection of link and fall-through address using a bit in a branch address
for the selection
A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at...
Apparatus and method for reducing precision of data
Methods and apparatus for reducing precision of an input signal, by comparing a portion of the input signal to a preselected threshold value, and determining a...
Timing based LNA gain adjustment in an RF receiver to compensate for
A Radio Frequency (RF) receiver includes a low noise amplifier (LNA) and a mixer coupled to the output of the LNA. The gain of the LNA is adjusted to maximize...
Very dense SRAM circuits
An SRAM cell eliminates the p-channel pull-up resistors to decrease its physical size. A tracking circuit generates a control signal used to ensure that the...
Single-ended-to-differential converter with common-mode voltage control
Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert...
Charge pump including a feedback device for use in a phase-locked loop
A charge pump circuit includes a high-swing transconductance amplifier. A high input swing transconductance is provided in a negative feedback loop of the charge...
Video and graphics system with parallel processing of graphics windows
A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple...
Method of near-unity fractional sampling rate alteration for high fidelity
The present invention provides an efficient method for near-unity sampling rate alteration in high performance applications, such as CD to DAT conversion....
Oscillator having multi-phase complementary outputs
An oscillator having multi-phase complementary outputs comprises a first plurality of single ended amplifiers connected in series to form an input and an output...
Variable rate modulator
Clock signals and digital data signals at a variable frequency are introduced to the input of a FIFO and are passed from the FIFO at a second (or intermediate)...
Delay generator with controlled delay circuit
A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay...
System and method to reduce noise in a substrate
A system and method for reducing noise in a substrate of a chip is provided. The system may include a substrate (70) doped with a first dopant. A first well (80)...
Replacement data error detector
A cache includes an error circuit for detecting errors in the replacement data. If an error is detected, the cache may update the replacement data to eliminate...
Transmitter method, apparatus, and frequency plan for minimizing spurious
A translational-loop transmitter includes a local oscillator (LO) generator for generating first and second LO signals, a modulator for generating a modulated...
Home phone line network architecture
Home phone line network devices, conforming to different versions of the standards, are interconnected and interoperable on a UTP transmission medium. Higher...
Synchronous data serialization circuit
In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first...
System, method, and apparatus for variable length decoder
A system method, and apparatus for decoding a bitstream comprising variable length coded symbols are presented herein. The bitstream is parsed and the symbols...
Class AB digital to analog converter/line driver
A differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors...
Voltage mode differential driver and method
A differential driver includes a switching module and first and second voltage controlled voltage sources. The switching module has a plurality of switches each...