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Patent # Description
US-6,848,912 Via providing multiple electrically conductive paths through a circuit board
A via provides a plurality of electrical connections between conductors on different layers of a circuit board. The via includes an opening through the circuit...
US-6,848,024 Programmably disabling one or more cache entries
A cache may be programmed to disable one or more entries from allocation for storing memory data (e.g. in response to a memory transaction which misses the...
US-6,848,012 Method and system for an adaptive multimode media queue
Embodiments of the invention may provide a method for implementing an adaptive multimode media queue. A mode of operation may be determined for a received media...
US-6,847,789 Linear half-rate phase detector and clock and data recovery circuit
Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate,...
US-6,847,686 Video encoding device
Video encoding device including a video input processor, for receiving said video signal, a global controller, for controlling the global operation of the video...
US-6,847,614 Apparatus and method for unilateral topology discovery in network management
A system for reducing the cost of network managment by using a proxy agent and subchannel communications so fewer SNMP licenses and fewer protocol stacks are...
US-6,847,282 Multiple layer inductor and method of making the same
A multiple layer inductor has a first spiral conductive pattern disposed on a first surface; a second spiral conductive pattern disposed on a second surface; a...
US-6,847,248 Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations
A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the...
US-6,845,232 Analog peak detection circuitry for radio receivers
A receiver portion of a radio includes an analog circuit for determining a peak amplitude in a way that eliminates or reduces the effects of frequency errors...
US-6,844,764 System and method for generating two effective frequencies using a single clock
A method and apparatus are disclosed for generating a second clock signal, having a second effective clock frequency, from a first clock signal, having a first...
US-6,844,755 Methods and systems for sensing and compensating for process, voltage, temperature, and load variations
Methods and systems for maintaining desired circuit and/or signal characteristics, such as impedance matching characteristics and rise and fall time...
US-6,844,226 System and method to reduce noise in a substrate
Aspects of the method for reducing noise in the substrate may comprise doping a substrate with a first dopant and doping a first well disposed on the substrate...
US-6,842,495 Dual mode QAM/VSB receiver
A television receiver system capable of receiving and demodulating television signal information content that has been modulated and transmitted in accordance...
US-6,842,457 Flexible DMA descriptor support
A method of processing DMA operations includes providing a DMA descriptor, with the DMA descriptor including a reload field therein. The DMA descriptor is then...
US-6,842,379 Non-volatile memory apparatus and method capable of controlling the quantity of charge stored in memory cells
A digital memory system (30) includes a memory cell (10), a bit line (12), a voltage generator (320) a controller (90) and a charge integrity estimating module...
US-6,842,130 Hardware-efficient implementation of dynamic element matching in sigma-delta DAC's
A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x.sub.0 and x.sub.1 of the input...
US-6,842,079 High-speed, high PSRR, wide operating range voltage controlled oscillator
A VCO for a PLL may include a ring oscillator having a power supply controlled in response to the VCO's control voltage input and an inverter having an input...
US-6,839,886 Method and apparatus for facilitating circuit design
There is disclosed a system for designing circuits which involves pre-placing delay elements between circuit components susceptible to shoot-through due to...
US-6,839,349 Mirroring in a stacked network switch configuration
A method of mirroring data to a mirrored to port in a plurality of switches. The method has the steps of determining if data was sent to all of said plurality of...
US-6,839,211 Methods and systems for reducing power-on failure of integrated circuits
Methods and systems for protecting integrated circuits ("ICs") from power-on sequence currents, including methods and systems for biasing transistors in paths...
US-6,839,005 Low memory and MIPS efficient technique for decoding Huffman codes using multi-stage, multi-bits lookup at...
Present herein is a low memory and MIPS efficient technique for decoding Huffman codes using multi-stage, multi-bits lookup at different levels. A binary tree is...
US-6,838,947 Apparatus and method for phase lock loop gain control using unit current sources
A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel...
US-6,838,937 Method and system for implementing autonomous automatic gain control in a low noise broadband distribution...
Provided is a system for implementing gain control in an amplification module comprising a first stage amplifier having a number of first stage input and output...
US-6,836,861 Efficient memory allocation scheme for data collection
A system and method that provides an integrated circuit which includes a small on-chip buffer to store collected data, thereby shifting the burden of storing the...
US-6,836,837 Register addressing
There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first...
US-6,836,234 System for matching rise and fall times of drive signals in a digital to analog converter
A system (e.g., a digital-to-analog converter (DAC)) includes a digital section and an analog section. The digital section has a driver portion that generates...
US-6,836,156 High frequency signal peak detector
A signal power detector includes an input coupling circuit and a rectifying operational amplifier. The input coupling circuit is operably coupled to receive a...
US-6,834,379 Timing path detailer
A method (and a computer accessible medium comprising one or more instructions which, when executed, implement the method) is contemplated. At least a first...
US-6,834,057 Cable modem system with sample and packet synchronization
A method of processing sampled voice packets from a voice packet sender for transmission over a bit-rate sampled data transmission system, such as by a cable...
US-6,833,763 CDR lock detector with hysteresis
A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to...
US-6,833,759 System and method for a programmable gain amplifier
Provided is system for an improved programmable gain amplifier (PGA). The system includes an amplifier and a first gain control mechanism. The first gain control...
US-6,833,756 Input buffer amplifier with centroidal layout
An input buffer amplifier has a symmetrical centroidal layout. The input buffer amplifier includes two half differential amplifiers that have substantially...
US-6,833,734 Line-driver with power down loopback protection
A line driver selectively drives one of two transmission lines. The line driver includes a differential amplifier connected to first and second differential...
US-6,833,604 High density metal capacitor using dual-damascene copper interconnect
An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process,...
US-6,832,078 Scaling adjustment using pilot signal
A demodulator (10) converts television signals to video baseband signals and audio baseband signals including stereo signals representing a right channel signal...
US-6,831,585 Distributed averaging analog to digital converter topology
An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in...
US-6,831,584 High-speed low-distortion analog-to digital converter
An analog to digital converter includes an array of differential input amplifiers. Each amplifier inputs an input voltage and a corresponding voltage reference,...
US-6,829,715 Multiprotocol computer bus interface adapter and method
A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time...
US-6,829,550 Calibration of received signal strength indication within a radio frequency integrated circuit
Calibration of received signal strength indication (RSSI) within a radio frequency integrated circuit (RFIC) begins by concurrently enables a transmitter portion...
US-6,828,926 Interspersed training for turbo coded modulation
A communications system, having a combination Reed-Solomon encoder and a Turbo-Code encoder Data frame configuration which may be changed to accommodate embedded...
US-6,828,866 High noise rejection voltage-controlled ring oscillator architecture
A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring...
US-6,828,860 Gigabit ethernet transceiver with analog front end
Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain...
US-6,828,854 Method and circuit for a dual supply amplifier
A circuit and method for bridging an analog signal between two integrated circuits operating at different supply voltages. The circuit is a two stage fixed gain...
US-6,828,654 Thick oxide P-gate NMOS capacitor for use in a phase-locked loop circuit and method of making same
In a low-pass filter for a phase locked loop (PLL) circuit, a capacitor formed by an N-type substrate, a P-type region formed on the N-type substrate, a thick...
US-6,826,561 Method and apparatus for performing a binary search on an expanded tree
A method and apparatus for searching an electronically stored table of information including a plurality of table entries and facilitating high speed searching...
US-6,826,242 Method for whitening colored noise in a communication system
A filter settings generation operation includes sampling colored noise present at the input of a receiver to produce a sampled signal. The sampled signal is...
US-6,826,165 Radio frequency local area network
An apparatus and a method for routing data in a radio data communication system having one or more host computers, one or more intermediate base stations, and...
US-6,825,108 Ball grid array package fabrication with IC die support structures
A system and method of assembling a ball grid array (BGA) package with IC die support is described. A stiffener is attached to a substrate that includes a...
US-6,823,483 Physical coding sublayer for a multi-pair gigabit transceiver
A physical coding sublayer (PCS) transmitter circuit generates encoded symbols based on a transmission standard. For example, in one embodiment, the transmission...
US-6,822,918 Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power...
The present invention relates to a method for improving speed and increasing performance in a multi-port register file memory or SRAM including at least one...
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