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Programmably disabling one or more cache entries
A cache may be programmed to disable one or more entries from allocation for storing memory data (e.g. in response to a memory transaction which misses the...
Method and system for an adaptive multimode media queue
Embodiments of the invention may provide a method for implementing an adaptive multimode media queue. A mode of operation may be determined for a received media...
Linear half-rate phase detector and clock and data recovery circuit
Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate,...
Video encoding device
Video encoding device including a video input processor, for receiving said video signal, a global controller, for controlling the global operation of the video...
Apparatus and method for unilateral topology discovery in network
A system for reducing the cost of network managment by using a proxy agent and subchannel communications so fewer SNMP licenses and fewer protocol stacks are...
Multiple layer inductor and method of making the same
A multiple layer inductor has a first spiral conductive pattern disposed on a first surface; a second spiral conductive pattern disposed on a second surface; a...
Sub-micron high input voltage tolerant input output (I/O) circuit which
accommodates large power supply variations
A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the...
Analog peak detection circuitry for radio receivers
A receiver portion of a radio includes an analog circuit for determining a peak amplitude in a way that eliminates or reduces the effects of frequency errors...
System and method for generating two effective frequencies using a single
A method and apparatus are disclosed for generating a second clock signal, having a second effective clock frequency, from a first clock signal, having a first...
Methods and systems for sensing and compensating for process, voltage,
temperature, and load variations
Methods and systems for maintaining desired circuit and/or signal characteristics, such as impedance matching characteristics and rise and fall time...
System and method to reduce noise in a substrate
Aspects of the method for reducing noise in the substrate may comprise doping a substrate with a first dopant and doping a first well disposed on the substrate...
Dual mode QAM/VSB receiver
A television receiver system capable of receiving and demodulating television signal information content that has been modulated and transmitted in accordance...
Flexible DMA descriptor support
A method of processing DMA operations includes providing a DMA descriptor, with the DMA descriptor including a reload field therein. The DMA descriptor is then...
Non-volatile memory apparatus and method capable of controlling the
quantity of charge stored in memory cells
A digital memory system (30) includes a memory cell (10), a bit line (12), a voltage generator (320) a controller (90) and a charge integrity estimating module...
Hardware-efficient implementation of dynamic element matching in
A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x.sub.0 and x.sub.1 of the input...
High-speed, high PSRR, wide operating range voltage controlled oscillator
A VCO for a PLL may include a ring oscillator having a power supply controlled in response to the VCO's control voltage input and an inverter having an input...
Method and apparatus for facilitating circuit design
There is disclosed a system for designing circuits which involves pre-placing delay elements between circuit components susceptible to shoot-through due to...
Mirroring in a stacked network switch configuration
A method of mirroring data to a mirrored to port in a plurality of switches. The method has the steps of determining if data was sent to all of said plurality of...
Methods and systems for reducing power-on failure of integrated circuits
Methods and systems for protecting integrated circuits ("ICs") from power-on sequence currents, including methods and systems for biasing transistors in paths...
Low memory and MIPS efficient technique for decoding Huffman codes using
multi-stage, multi-bits lookup at...
Present herein is a low memory and MIPS efficient technique for decoding Huffman codes using multi-stage, multi-bits lookup at different levels. A binary tree is...
Apparatus and method for phase lock loop gain control using unit current
A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel...
Method and system for implementing autonomous automatic gain control in a
low noise broadband distribution...
Provided is a system for implementing gain control in an amplification module comprising a first stage amplifier having a number of first stage input and output...
Efficient memory allocation scheme for data collection
A system and method that provides an integrated circuit which includes a small on-chip buffer to store collected data, thereby shifting the burden of storing the...
There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first...
System for matching rise and fall times of drive signals in a digital to
A system (e.g., a digital-to-analog converter (DAC)) includes a digital section and an analog section. The digital section has a driver portion that generates...
High frequency signal peak detector
A signal power detector includes an input coupling circuit and a rectifying operational amplifier. The input coupling circuit is operably coupled to receive a...
Timing path detailer
A method (and a computer accessible medium comprising one or more instructions which, when executed, implement the method) is contemplated. At least a first...
Cable modem system with sample and packet synchronization
A method of processing sampled voice packets from a voice packet sender for transmission over a bit-rate sampled data transmission system, such as by a cable...
CDR lock detector with hysteresis
A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to...
System and method for a programmable gain amplifier
Provided is system for an improved programmable gain amplifier (PGA). The system includes an amplifier and a first gain control mechanism. The first gain control...
Input buffer amplifier with centroidal layout
An input buffer amplifier has a symmetrical centroidal layout. The input buffer amplifier includes two half differential amplifiers that have substantially...
Line-driver with power down loopback protection
A line driver selectively drives one of two transmission lines. The line driver includes a differential amplifier connected to first and second differential...
High density metal capacitor using dual-damascene copper interconnect
An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process,...
Scaling adjustment using pilot signal
A demodulator (10) converts television signals to video baseband signals and audio baseband signals including stereo signals representing a right channel signal...
Distributed averaging analog to digital converter topology
An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in...
High-speed low-distortion analog-to digital converter
An analog to digital converter includes an array of differential input amplifiers. Each amplifier inputs an input voltage and a corresponding voltage reference,...
Multiprotocol computer bus interface adapter and method
A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time...
Calibration of received signal strength indication within a radio frequency
Calibration of received signal strength indication (RSSI) within a radio frequency integrated circuit (RFIC) begins by concurrently enables a transmitter portion...
Interspersed training for turbo coded modulation
A communications system, having a combination Reed-Solomon encoder and a Turbo-Code encoder Data frame configuration which may be changed to accommodate embedded...
High noise rejection voltage-controlled ring oscillator architecture
A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring...
Gigabit ethernet transceiver with analog front end
Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain...
Method and circuit for a dual supply amplifier
A circuit and method for bridging an analog signal between two integrated circuits operating at different supply voltages. The circuit is a two stage fixed gain...
Thick oxide P-gate NMOS capacitor for use in a phase-locked loop circuit
and method of making same
In a low-pass filter for a phase locked loop (PLL) circuit, a capacitor formed by an N-type substrate, a P-type region formed on the N-type substrate, a thick...
Method and apparatus for performing a binary search on an expanded tree
A method and apparatus for searching an electronically stored table of information including a plurality of table entries and facilitating high speed searching...
Method for whitening colored noise in a communication system
A filter settings generation operation includes sampling colored noise present at the input of a receiver to produce a sampled signal. The sampled signal is...
Radio frequency local area network
An apparatus and a method for routing data in a radio data communication system having one or more host computers, one or more intermediate base stations, and...
Ball grid array package fabrication with IC die support structures
A system and method of assembling a ball grid array (BGA) package with IC die support is described. A stiffener is attached to a substrate that includes a...
Physical coding sublayer for a multi-pair gigabit transceiver
A physical coding sublayer (PCS) transmitter circuit generates encoded symbols based on a transmission standard. For example, in one embodiment, the transmission...
Very small swing high performance asynchronous CMOS static memory
(multi-port register file) with power...
The present invention relates to a method for improving speed and increasing performance in a multi-port register file memory or SRAM including at least one...
Dynamic scan circuitry for B-phase
A first dynamic logic circuit has an output node on which a scan value is provided during scan. One of one or more second dynamic logic circuits has an input...