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Gain control methods and systems in an amplifier assembly
A Variable Gain Amplifier (VGA) amplifies an input signal according to a gain, to produce an amplified signal. A detector module detects a power indicative of a...
Gigabit ethernet transceiver with analog front end
Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain...
Circuit for asynchronous reset in current mode logic circuits
A current mode logic (CML) flip flop includes a first CML latch and a second CML latch. A plurality of pull-up switches are responsive to a reset signal. Outputs...
Method of creating incentives for establishing hotspot locations
A process of creating incentives for wireless hotspots by a service provider is disclosed. An access point is provided to a wireless hotspot for wireless devices...
High performance self balancing low cost network switching architecture
based on distributed hierarchical shared
A communications component comprises a first data port interface supporting a plurality of data ports transmitting and receiving data. A second data port...
Method and system for more efficiently utilizing processors of a graphics
A method and system for utilizing processor(s) and bypass processor(s) of a computer graphics system are disclosed. The processor(s) and bypass processor(s)...
Method and system for rendering macropixels in a graphical image
A method and system for providing a graphical image on a display is disclosed. The display includes a plurality of pixels. The data includes a plurality of...
System and method to substantially eliminate glitch in a digital to analog
A system (e.g., a digital-to-analog converter (DAC)) includes a digital section and an analog section. The digital section has drivers that generate drive...
Hardware-efficient implementation of dynamic element matching in
A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x.sub.0 and x.sub.1 of the input...
Gain scaling for higher signal-to-noise ratios in multistage, multi-bit
delta sigma modulators
An n-bit quantizer of a downstream modulator stage is configured to produce an n-bit quantized signal from an analog signal having a range. The n-bit quantizer...
Low jitter high speed CMOS to CML clock converter
Provided is a circuit to convert input CMOS level signals having a predetermined duty cycle to CML level signals having a higher duty cycle. The circuit includes...
Apparatus and method for managing memory defects
A method and apparatus for managing defects in a memory, wherein the method includes the steps of testing a plurality of memory locations to determine an...
Fir filter tap architecture for highly dense layout
An area-efficient finite impulse response filter having permuted bit-order functional elements that provide substantially straight and direct interconnects with...
Antenna connectors for computer devices utilizing radio and modem cards
A radio card sized for insertion into an electronic device. The radio card includes a housing; a radio circuit disposed within the housing; an internal antenna...
Startup protocol for high throughput communications systems
A startup protocol is provided for use in a communications system having a communications line with a master transceiver at a first end and a slave transceiver...
Virtual gateway system and method
Existing (already installed) plain old telephone service (POTS) wiring at a customer premises is used as the wiring infrastructure for a local area network and...
Method for determining when a communication device should rate shift or
roam in a wireless environment
Methods for improving communication performance in a wireless communication system where the wireless communication system has at least one mobile wireless...
Compact balun with rejection filter for 802.11a and 802.11b simultaneous
A balancing/unbalancing (balun) structure for operating at frequency f.sub.1 includes a microstrip printed circuit board (PCB). A balun on the PCB includes two...
Method and apparatus for efficient mixed signal processing in a digital
A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate...
Phase interpolator device and method
A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at...
Low jitter high phase resolution PLL-based timing recovery system
A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency...
Hardware and software programmable fuses for memory repair
The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable...
Modeling miller effect in static timing analysis
A method is contemplated. According to the method, capacitances in a first resistance/capacitance (RC) extraction corresponding to a circuit are modified. Each...
Method and system for fast data access using a memory array
First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits....
System and method for programming non-volatile memory
Systems and methods that may program a non-volatile memory for use in configuring features of a device, such as a set top box, for example, are disclosed. One...
Method for the suppression and expansion of packet header information in
cable modem and cable modem...
Data packets transmitted over a cable network are suppressed by hardware at the transmitting end and expanded on the receiving end. This conserves bandwidth as...
High speed analog to digital converter
An analog to digital converter includes a reference ladder, a track-and-hold amplifier tracking an input signal with its output signal during the phase...
Wide common mode differential input amplifier and method
A wide input range amplifier includes a first and second stage. The first stage has first and second inputs, first and second outputs, and first, second and...
In-place data transformation for fault-tolerant disk storage systems
A fault tolerant method transforms physically contiguous data in-place on a disk by partitioning the physically contiguous data into an empty region physically...
Use of tags to cancel a conditional branch delay slot instruction
A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot...
Method and apparatus for latency reduction in low power two way
communications equipment applications in hybrid...
A two way communication system is adapted to reduce latency while the communications system is operating in a low power mode. The two way communication system...
Content addressable memory with power reduction technique
A CAM may include a plurality of CAM cells. Each CAM cell is configured to generate an output indicating if a corresponding input bit and the bit stored in that...
Analog to digital converter with interpolation of reference ladder
An N-bit analog to digital converter includes a reference ladder connected to an imput voltage at one end, and to ground at another end, an array of differential...
Conditional clock buffer circuit
A conditional clock buffer circuit includes a clock output and is coupled to receive a clock input and a condition signal. The conditional clock buffer circuit...
Method and system for reducing cross-talk and avoiding bridged taps
The present invention establishes a communications link between a central office (CO) modem and a customer premise equipment (CPE) modem. The CO modem then...
Self-repairing built-in self test for linked list memories
One of a linked list memories is selected as a defect marking memory and faults in rows of the defect marking memory are detected. Row addresses having at least...
The present invention relates to a system and method for processing information, specifically data packets. One embodiment of the present invention relates to a...
Method and system for producing a drive signal for a current steering
Provided is a method and system for producing a drive signal for a current steering amplifier. An exemplary method comprises receiving a supply voltage signal...
Switched-capacitor, common-mode feedback circuit for a differential
amplifier without tail current
Provided is a switched capacitor feedback circuit including two or more input ports configured to receive a corresponding a number of input signals and at least...
Sense amplifier with offset cancellation and charge-share limited swing
A sense amplifier adapted to sense an input signal on global bitlines, having an amplifier offset cancellation network and an offset equalization network. The...
Symmetric differential logic circuits
Embodiments of the present invention perform logical operations utilizing a symmetric logic circuit comprising two logic units. In a symmetric logic circuit, the...
System and method for hardware based reassembly of a fragmented packet
A system and method for hardware based reassembly of a fragmented packet is shown. The method includes receiving a bandwidth request to transfer a data packet...
Subdimensional single-carrier modulation
A method for modulating a sequence of data symbols such that the transmit signal exhibits spectral redundancy. Null symbols are inserted in the sequence of data...
Multi-pair gigabit ethernet transceiver
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver...
Receiver architecture employing low intermediate frequency and complex
A communications receiver architecture characterized by a relatively low intermediate frequency (IF) and a polyphase filter. The receiver includes an input...
Method and system for providing a hardware sort for a large number of items
A method and system for sorting a number of items in a computer system is described. The sort is based on values of a key. Each item has a value. The method and...
Bad frame indicator for radio telephone receivers
A method for identifying a bad GSM speed frame and simultaneously maintaining a frame erasure rate below a specified value. The method is based upon a joint use...
Equalization and decision-directed loops with trellis demodulation in high
Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver...
Method and system for providing implicit edge antialiasing
A method and system for providing antialiasing of a graphical image on a display from data describing at least one object is disclosed. The display includes a...
Methods and systems for digital dither
Methods and systems for applying digital dither includes methods and systems for applying digital dither in data converters, such as, for example, delta-sigma...