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Timing recovery using the pilot signal in high definition TV
Improved carrier recovery and symbol timing systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system is disclosed. Carrier and...
Sense amplifier with adaptive reference generation
A digital memory system (30) includes a memory cell (52), a bit line (50), a transfer gate (60) a reference voltage generator (40), a sense amplifier (70) and a...
Row-column repair technique for semiconductor memory arrays
A method for locating a repair solution for a memory that includes a memory array containing a plurality of rows and a plurality of columns, N redundant rows,...
Electrostatic protection circuit with impedance matching for radio
frequency integrated circuits
An electrostatic-discharge/impedance-matching circuit for use in radio frequency (RF) integrated circuits. The electrostatic-discharge/impedance-matching circuit...
Method and system for performing PAL luma two line vertical combing
A method and system for performing combing for PAL luma data is disclosed. The combing is performed for a display having a plurality of lines. The display is...
Method and apparatus for mismatched shaping of an oversampled converter
Methods and apparatuses for spectrally shaping mismatch errors in a multi-bit digital to analog converter (DAC). In an embodiment, the multi-bit DAC is...
Programmable variable-length decoder
System and method for decoding variable-length codes. A variable-length decoder includes an address generator and a local memory unit. The local memory stores a...
Single-ended-to-differential converter with common-mode voltage control
Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert...
Series terminated CMOS output driver with impedance calibration
A differential line driver includes a plurality of driver cells. Control logic outputs positive and negative control signals to the driver cells so as to match a...
Multi-power ring chip scale package for system level integration
A scalable multi-power integrated circuit package for integrated circuits having spaced apart first, second and third pluralities of respective spaced apart chip...
Integrated fuse with regions of different doping within the fuse neck
An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The...
Video and graphics system with video scaling
A video and graphics system has a reduced memory mode in which video images are reduced in half in horizontal direction during decoding. The video and graphics...
Active impedance matching in communications systems
A signal sensing module senses an RF signal and produces one or more secondary signals representative of the RF signal. An impedance matching control module...
Method and apparatus for circuit design
A method for designing multi-layer electronic circuits includes defining a plurality of circuit blocks in terms of physical boundaries, the plurality of circuit...
System on a chip for networking
A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and...
Method and interface for improved efficiency in performing bus-to-bus read
A novel method and interface is provided for conducting read data transfers between an initiator device on a single-transaction bus and a target device on a...
Gateway with voice
In one aspect of the present invention, a network gateway is configured to facilitate on line and off line bi-directional communication between a number of near...
Method and apparatus for efficient mixed signal processing in a digital
A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate...
Methods and systems for limiting supply bounce
Methods and systems for limiting power supply and ground bounce enables control of the output current drive dependent on the changes in supply (VDD and GND)...
Cable modem system with sample and packet synchronization
A method for communicating information is disclosed wherein a time slot is allocated in a time division multiple access system for a transmission from a...
A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics...
Graphics processor, system and method for generating screen pixels in
raster order utilizing a single interpolator
A method and system for generating a graphical display from data describing at least one three-dimensional object is disclosed. The method and system include...
Shuffler apparatus and related dynamic element matching technique for
linearization of unit-element...
A data shuffler apparatus shuffles input bits to perform dynamic element matching. The shuffler apparatus includes N input shufflers, each input shuffler having...
Scalable gray code counter and applications thereof
A non-power-of-two modulo N Gray-code counter (the "Gray-code counter") and a binary incrementer-decrementer algorithm are disclosed. One embodiment of the...
System and method for automatic parameter adjustment within a phase locked
A signal recovery system and methods to quickly acquire signal lock and maintain consistent performance of the signal recovery system for different signal input...
Method and apparatus for frequency shift-keying demodulation and
A method and apparatus for frequency shift-keying (FSK) demodulation includes processing that begins by generating a charge signal, a data acquisition signal,...
CMOS lock detect with double protection
Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device...
Jitter suppression techniques for laser driver circuits
Driver circuits of the present invention provide current to drive laser diodes. The output current of the driver circuit includes a data signal and a low...
Off-line broadband network interface
A network interface is presented that receives packet data from a shared medium and accomplishes the signal processing required to convert the data packet to...
Method and apparatus for the synchronization of multiple cable modem
termination system devices
A plurality of CMTS devices are linked together and synchronized to facilitate communication between the respective CMTS devices and respective downstream cable...
Distributed, highly configurable modular predecoding
The present invention relates to a system and method for providing distributed, highly configurable modular predecoding. The system includes a hierarchical...
On-chip differential multi-layer inductor
An on-chip differential multi-layer inductor includes a 1.sup.st partial winding on a 1.sup.st layer, a 2.sup.nd partial winding on the 1.sup.st layer, a...
Large gain range, high linearity, low noise MOS VGA
An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides...
Packet based network exchange with rate synchronization
A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a...
Video encoding device
A video encoding system includes a video source providing a multiple frame video signal, a compressed data interface, a host interface and a video encoding...
Operational amplifier with increased common mode input range
An operational amplifier includes a first stage with a first differential transistor pair inputting a differential input signal at their gates, a first tail...
Clock multiplier using masked control of clock pulses
A clock multiplier circuit is receives an input signal and generates a clock output signal. The clock multiplier circuit generates a number of pulses to be used...
High speed differential signaling logic gate and applications thereof
A high-speed differential signaling logic gate includes a 1.sup.st input transistor, 2.sup.nd input transistor, complimentary transistor, complimentary...
Balanced linked lists for high performance data buffers in a network device
A process of handling packet data in a packet buffer is disclosed. Free pointers are stored in a plurality of free pointer queues, with each of the plurality...
Switching between decoded image channels
An image data decoding system (2) is described in which a stream of compressed image data (1) corresponding to a plurality of image channels (ChA, ChB, ChC) each...
Configurable multi-port modem to achieve a high bit rate in a DSL system
A configurable multi-port modem includes a plurality of hybrids, a plurality of receivers, a plurality of transmitters, and a switching module. Each of the...
Refresh techniques for memory data retention
A digital memory system (30) includes a memory cell (52), a bit line (50) and a charge integrity estimating module 35. The module is operative during a first...
Printed antenna and applications thereof
A printed antenna includes a 1.sup.st dipole section and a 2.sup.nd dipole section. The 1.sup.st dipole section includes a 1.sup.st radiation section and a...
Universal single-ended parallel bus
A high speed data communication system uses a single-ended bus architecture with a reference signal extracted from a differential periodic signal that is...
Local control of multiple context processing elements with configuration
A method and apparatus for providing local control of processing elements in a network of multiple context processing elements (MCPEs). A MCPE stores...
Efficient excitation quantization in noise feedback coding with general
In a Noise Feedback Coding (NFC) system having a corresponding ZERO-STATE filter structure, the first ZERO-STATE filter structure including multiple filters, a...
Dense content addressable memory cell
A content addressable memory cell (10) comprises a word line 12, a first bit line (14), and a second bit line (16). A pair of transistors (30-31) is arranged to...
Gain scaling for higher signal-to-noise ratios in multistage, multi-bit
delta sigma modulators
Gain scaling of multistage, multi-bit delta sigma modulators for higher signal-to-noise ratios. In a multistage delta sigma modulator having a modulator stage...
Multi-level hierarchial radio-frequency system communication system
Portable measuring devices which communicate by low power transceivers through a communication controller with a printer device collect weight and size data on...
A random number generator circuit includes a primary circuit configured to generate a value within a first range and a secondary circuit configured to generate a...