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Patent # Description
US-6,748,492 Deterministic setting of replacement policy in a cache through way selection
A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a way of the cache. The cache may alter the...
US-6,748,479 System having interfaces and switch that separates coherent and packet traffic
An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory...
US-6,748,041 GM cell based control loops
Various circuit techniques employ a transconductance (gm) cell in control loops to implement circuits such as phase locked loops and delay locked loops that are...
US-6,747,996 Synchronized transport across non-synchronous networks
A method of providing for synchronizing one or more synchronous terminals with one or more synchronous endpoints, each synchronous terminal and each synchronous...
US-6,747,664 Method and system for efficiently using fewer blending units for antialiasing
A system and method for providing antialiasing of a graphical image on a display is disclosed. The graphical image is generated from data describing at least one...
US-6,747,518 CDR lock detector with hysteresis
A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to...
US-6,747,510 Apparatus, system, and method for amplifying a signal, and applications thereof
An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is...
US-6,747,497 High speed, wide bandwidth phase locked loop
A PLL may include a voltage regulator for providing a regulated voltage to one or more PLL components (e.g. a charge pump, a voltage controlled oscillator,...
US-6,745,354 Memory redundancy implementation
In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having...
US-6,745,317 Three level direct communication connections between neighboring multiple context processing elements
A method and an apparatus for configuration of multiple context processing elements (MCPEs)are described. According to one aspect of the invention, the structure...
US-6,745,297 Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent
A system may include two or more agents, at least some of which may cache data. In response to a read transaction, a caching agent may snoop its cached data and...
US-6,744,831 Adaptive electronic transmission signal cancellation apparatus for full duplex communication
An adaptive electronic transmission signal cancellation circuit for separating transmit data from receive data in a bidirectional communication system operating...
US-6,744,660 High voltage switch circuitry
The present invention relates to a method of setting a state of a one-time programmable memory device having at least one memory cell with a thin gate-ox fuse...
US-6,744,472 Graphics display system with video synchronization feature
A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video...
US-6,744,320 Variable transconductane variable gain amplifier utilizing a degenerated differential pair
Continuously tuning a transconductance. Coupling a degeneration resistance from a first source of a first transistor in a differential pair of transistors to a...
US-6,741,664 Low-latency high-speed trellis decoder
A method for decoding a word received at a current time instant into a symbol of a trellis code. The trellis code corresponds to a trellis diagram having N...
US-6,741,645 Technique for minimizing decision feedback equalizer wordlength in the presence of a DC component
A system for reducing the complexity of an adaptive decision feedback equalizer, for use in connection with a dual-mode QAM/VSB receiver system is disclosed. QAM...
US-6,741,243 Method and system for reducing overflows in a computer graphics system
A method and system for providing a graphical image on a display of a system is disclosed. The graphical image is provided from data describing a plurality of...
US-6,741,112 Input circuit with hysteresis
An input circuit has hysteresis to mitigate the effects of input noise. The input circuit receives an analog input signal and determines whether the unregulated...
US-6,738,833 Network device having a flexible EEPROM for setting configuration settings
A method for flexibly configuring default values of a network device and a network device using such flexible configuration method is described. First, it is...
US-6,738,601 Adaptive radio transceiver with floating MOSFET capacitors
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local...
US-6,738,419 Dynamic regulation of power consumption of a high-speed communication system
A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric...
US-6,738,072 Graphics display system with anti-flutter filtering and vertical scaling feature
A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video...
US-6,738,000 Calibration method for a digital-to-analogue converter using an array of current sources
A current source DAC has calibration of the current sources used for providing the analog output. There are two outputs, one of which provides the output current...
US-6,737,898 High speed flip-flop
A static latch can be converted to a dynamic latch by closing a pair of switches. When the switches are open, a first pair of back-to-back transistors serves as...
US-6,737,859 Dynamic register with IDDQ testing capability
The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating...
US-6,735,679 Apparatus and method for optimizing access to memory
A method and apparatus for optimizing access to memory, wherein the method includes the steps of receiving a first request for access to a memory, receiving at...
US-6,735,302 DSP based SLIC architecture with current-sensing voltage synthesis impedance matching and DC feed control
A CODEC and a SLIC assembly perform current-sensing-voltage synthesis impedance matching and DC feed control functions. Signal processing that does not require...
US-6,735,135 Compact analog-multiplexed global sense amplifier for RAMs
The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. The...
US-6,732,234 Direct access mode for a cache
A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response...
US-6,731,914 Determination of transmitter distortion
The present invention provides a method for determining nonlinear distortion of a transmitter. A test symbol sequence is transmitted from the transmitter under...
US-6,731,691 Multi-pair gigabit ethernet transceiver having adaptive disabling of circuit elements
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver...
US-6,731,296 Method and system for providing programmable texture processing
A method and system for processing textures for a graphical image on a display is disclosed. The graphical image includes an object. The object includes a...
US-6,731,295 Graphics display system with window descriptors
A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video...
US-6,731,160 Adjustable bandwidth high pass filter for large input signal, low supply voltage applications
Often programmable gain attenuators (PGAs) are combined with high pass filters. Adjustment of the highpass filter however can have unintended effects, such as...
US-6,728,130 Very dense SRAM circuits
An SRAM cell eliminates the p-channel pull-up resistors to decrease its physical size. A tracking circuit generates a control signal used to ensure that the...
US-6,727,936 NTSC interference rejection filter
An electronic, programmable filter is disclosed which selectively removes interference, noise or distortion components from a frequency band without perturbing...
US-6,727,839 High speed, low power comparator
A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in...
US-6,727,756 Single-ended-to-differential converter with common-mode voltage control
Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert...
US-6,727,729 Linear buffer
A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output...
US-6,727,602 Power supply for controlled parallel charging and discharging of batteries
A power supply and switching technique is provided that utilizes a first battery and a second battery to charge a load. The power supply includes a first...
US-6,725,408 Built-in self-test for multi-channel transceivers without data alignment
A method and device for testing multi-channel transceivers in an integrated circuit is provided. More specifically, the present invention relates to a method and...
US-6,724,681 Asynchronously-resettable decoder with redundancy
A decoder providing asynchronous reset, redundancy, or both an asynchronously-resettable decoder with redundancy. The decoder has a synchronous portion,...
US-6,724,335 Systems and methods for digital upconversion for television signals
Systems and methods for digital upconversion of baseband television signals that can be used in cable television headend systems are provided. In one embodiment,...
US-6,721,916 System and method for trellis decoding in a multi-pair transceiver system
A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional...
US-6,721,837 Graphics display system with unified memory architecture
A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video...
US-6,721,380 Fully differential CMOS phase-locked loop
The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL)...
US-6,720,897 State-delayed technique and system to remove tones of dynamic element matching
A filter structure used with a dynamic element matching encoder for a sigma-delta digital-to-analog converter is presented. A sampled input sequence having...
US-6,720,894 Method of and system for performing differential lossless compression
A method of decompressing data words of an instruction set includes: A. filling a primary dictionary with at least one primary data word of the instruction set,...
US-6,720,821 Methods and systems for generating interim voltage supplies
Methods and systems for protecting integrated circuits ("ICs") from power-on sequencing problems provide an interim voltages during power-on sequences in order...
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