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Patent # Description
US-6,690,726 Video encoding and video/audio/data multiplexing device
A buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for a proficient division of...
US-6,690,216 System and method for compensating for supply voltage induced clock delay mismatches
Various systems and methods providing clock delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog...
US-6,690,199 Methods and systems for providing load-adaptive output current drive
Methods and systems for sensing load conditions and for adjusting output current drive according to the sensed load conditions to maintain one or more signal...
US-6,686,853 Method and apparatus for iterative decoding
Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative...
US-6,686,775 Dynamic scan circuitry for B-phase
A first dynamic logic circuit has an output node on which a scan value is provided during scan. One of one or more second dynamic logic circuits has an input...
US-6,686,772 Voltage mode differential driver and method
A differential driver includes a switching module and first and second voltage controlled voltage sources. The switching module has a plurality of switches each...
US-6,684,364 Forward error corrector
A method for decoding an algebraic-coded message including determining a discrepancy indicator; determining an error locator polynomial according to a modified...
US-6,684,296 Source controlled cache allocation
A cache is coupled to receive an access which includes a cache allocate indication. If the access is a miss in the cache, the cache either allocates a cache...
US-6,684,065 Variable gain amplifier for low voltage applications
An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled...
US-6,683,498 Protection circuit for extending headroom with off-chip inductors
A protection circuit for extending the dynamic range of an amplifier circuit is described. Off-chip impedances, such as inductors, cause the output of the...
US-6,681,302 Page open hint in transactions
A system including an agent and a memory controller, in which the agent may initiate transactions targeting a memory to which the memory controller is coupled...
US-6,680,650 MOSFET well biasing scheme that migrates body effect
A biasing scheme for a MOSFET that mitigates the MOSFET body effect. The biasing scheme can be realized replicating the voltage at the source terminal of a...
US-6,680,640 High linearity large bandwidth, switch insensitive, programmable gain attenuator
An apparatus for providing a programmable gain attenuator (PGA) while minimizing the influence of semiconductor switches on the signal being attenuated. An...
US-6,678,767 Bus sampling on one edge of a clock signal and driving on another edge
An agent may be coupled to receive a clock signal associated with the bus, and may be configured to drive a signal responsive to a first edge (rising or falling)...
US-6,678,198 Pseudo differential sensing method and apparatus for DRAM cell
Present invention describes an efficient implementation of differential sensing in single ended DRAM arrays. According to one embodiment of the present...
US-6,677,818 Method and circuit for a dual supply amplifier
A circuit and method for bridging an analog signal between two integrated circuits operating at different supply voltages. The circuit is a two stage fixed gain...
US-6,675,289 System and method for executing hybridized code on a dynamically configurable hardware environment
A system and method for executing previously created run time executables in a configurable processing element array is disclosed. In one embodiment, this system...
US-6,674,823 Variable rate modulator
Digital data signals at a variable input frequency are converted by a numerically controlled oscillator and an interpolator to a signal at a fixed output...
US-6,674,671 Circuit for lines with multiple drivers
An apparatus may include at least a first transistor, a second transistor, and a circuit. The first transistor has a first control terminal coupled to receive a...
US-6,674,389 Capacitive folding circuit for use in a folding/interpolating analog-to-digital converter
An M-bit folding/interpolating analog-to-digital converter (ADC) circuit, comprising a reference voltage generator, a converter, an interpolator, an amplifying...
US-6,674,388 High speed analog to digital converter
An analog to digital converter includes a reference ladder, a track-and-hold amplifier tracking an input signal with its output signal during the phase...
US-6,671,816 System and method for independent power sequencing of integrated circuits
A circuit for applying power to mixed mode integrated circuits in a predefined sequence. The circuit includes a first circuit powered by a first voltage and a...
US-6,671,342 Phase detectors in carrier recovery for offset QAM and VSB
Improved carrier recovery, symbol timing, and carrier phase tracking systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system...
US-6,671,216 Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low...
A ROM or other memory may include two or more partitions and a precharge circuit. Each of the partitions may be coupled to separate sets of output conductors, to...
US-6,670,848 Method and system for implementing autonomous automatic gain control in a low noise broadband distribution...
Provided is a system for implementing gain control in an amplification module comprising a first stage amplifier having a number of first stage input and output...
US-6,670,821 Methods and systems for sensing and compensating for process, voltage, temperature, and load variations
Methods and systems for maintaining desired circuit and/or signal characteristics, such as impedance matching characteristics and rise and fall time...
US-6,667,654 Biasing scheme for low supply headroom applications
Methods and apparatus for improving the current matching within current mirror circuits in applications such as low voltage integrated circuits. Embodiments of...
US-6,665,536 Local area network having multiple channel wireless access
A communication network having at least one access point supports wireless communication among a plurality of wireless roaming devices via a first and a second...
US-6,664,910 Distributed averaging analog to digital converter topology
An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in...
US-6,662,292 Memory access system
A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two...
US-6,661,727 Dynamic register with low clock rate testing capability
A method for refreshing data in a circuit element included in a dynamic register. A static loop is coupled to the circuit element as a feedback path from the...
US-6,661,427 Graphics display system with video scaler
A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video...
US-6,661,422 Video and graphics system with MPEG specific data transfer commands
A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data...
US-6,661,362 Methods and systems for high speed quantizers
Methods and systems for improved feedback processing in delta-sigma modulators, including single bit and multi-bit delta-sigma modulators, continuous-time and...
US-6,661,360 Analog to digital converter that services voice communications
An Analog-to-Digital-Converter (ADC) converts an analog signal to digital data. The ADC includes a modulator, a decimation filter, and a time dither clock...
US-6,661,261 Programmable divider with built-in programmable delay chain for high-speed/low power application
A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock...
US-6,658,016 Packet switching fabric having a segmented ring with token based resource control protocol and output queuing...
A packet switching fabric includes means forming a data ring, means forming a control ring, and means forming a plurality of data communication network links...
US-6,657,503 High noise rejection voltage-controlled ring oscillator architecture
A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring...
US-6,657,491 System and method for activating gain stages in an amplification module
A system is provided for activating gain stages in an amplification module. The system includes an amplification module including a first group of amplifiers....
US-6,657,462 Conditional clock buffer circuit
A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a...
US-6,654,378 Transaction control system including portable data terminal and mobile customer service station
A communication system including a battery powered mobile service station is used to provide transactional support within a premises. The mobile service station...
US-6,653,966 Subranging analog to digital converter with multi-phase clock timing
An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a...
US-6,653,901 System and method for a startup circuit for a differential CMOS amplifier
A system is provided for correcting start-up deficiencies in an amplifier. The system includes a comparing device configured to (i) receive a second circuit node...
US-6,653,876 Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL)
A method and apparatus are disclosed for efficiently doubling a first frequency of a first clock signal. A second clock signal at a second frequency is generated...
US-6,650,880 Wireless data communications using FIFO for synchronization memory
A wireless (radio) receiver receives RF signals carrying data synchronized with a first clock. The wireless receiver demodulates the RF signals to extract the...
US-6,650,624 Cable modem apparatus and method
A number of features for enhancing the performance of a cable transmission system in which data is transmitted between a cable modem termination system at a...
US-6,650,572 Compact analog-multiplexed global sense amplifier for rams
The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. As a...
US-6,650,563 Compact and highly efficient DRAM cell
A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing,...
US-6,650,267 Analog to digital converter
The output of each cell in an A-D converter on an IC chip is dependent upon the relative values of an input voltage and an individual one of progressive...
US-6,650,196 Multi-frequency band controlled oscillator
A variable frequency output signal is generated in response to a control signal by providing an oscillator (50) that generates the output signal in different...
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