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| Patent # | Description |
|---|---|
| US-6,650,167 |
Multi-level/single ended input level shifter circuit Systems and methods are disclosed for a multi-level level shifter circuit having a single ended input and adapted to translate one or more signals from one... |
| US-6,646,954 |
Synchronous controlled, self-timed local SRAM block The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local... |
| US-6,646,899 |
Content addressable memory with power reduction technique A CAM may include a plurality of CAM cells. Each CAM cell is configured to generate an output indicating if a corresponding input bit and the bit stored in that... |
| US-6,646,509 |
Layout technique for matched resistors on an integrated circuit substrate Provided a method of reducing impedance variations in an electrical circuit structured and arranged for placement on an integrated circuit (IC) substrate. The... |
| US-6,646,488 |
Delay circuit with delay relatively independent of process, voltage, and
temperature variations Methods and systems for controlling delay relatively independent of process, supply-voltage, and/or temperature ("PVT") variations include sensing an output... |
| US-6,643,595 |
System and method for detecting a device requiring power A system and technique for detecting a device that requires power is implemented with a power detection station. The power detection system includes a detector... |
| US-6,643,261 |
High performance self balancing low cost network switching architecture
based on distributed hierarchical... A data switch for network communications includes at least one first data port interface which supports a plurality of data ports which transmit and receive data... |
| US-6,642,762 |
Method and apparatus to ensure DLL locking at minimum delay A method and apparatus to ensure DLL locking at a minimum delay is provided. In one embodiment, a DLL circuit includes a phase detector, a counter, a... |
| US-6,640,288 |
Read exclusive for fast, simple invalidate An agent, in response to a write to a shared block, is configured to initiate a read exclusive transaction on an interface on which the agent communicates.... |
| US-6,639,866 |
Very small swing high performance asynchronous CMOS static memory
(multi-port register file) with power... The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate ... |
| US-6,639,530 |
Modulation of an analog signal into a digital representation thereof A method and apparatus for modulating a signal into a digital representation thereof includes processing that begins by integrating a difference between an input... |
| US-6,639,479 |
Highly stable integrated time reference An integrated oscillator that may be used as a time clock includes circuitry that oscillates about an RC time constant, which RC time constant is adjustable to... |
| US-6,639,478 |
Apparatus and method for reducing phase noise in oscillator circuits A resonant oscillator circuit includes an active device and a resonator that causes the active device to oscillate at a resonant frequency of the resonator. The... |
| US-6,639,443 |
Conditional clock buffer circuit A conditional clock buffer circuit includes a clock output and is coupled to receive a clock input and a condition signal. The conditional clock buffer circuit... |
| US-6,639,430 |
High speed latch comparators In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal... |
| US-6,636,222 |
Video and graphics system with an MPEG video decoder for concurrent
multi-row decoding A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV... |
| US-6,636,091 |
System and method for compensating for supply voltage induced clock delay
mismatches Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog... |
| US-6,633,952 |
Programmable refresh scheduler for embedded DRAMs In one aspect, the invention describes a mechanism for refreshing multiple memory words (rows) per refresh cycle, the number of simultaneously refreshed rows... |
| US-6,633,938 |
Independent reset of arbiters and agents to allow for delayed agent reset A system includes two or more agents and a distributed arbitration scheme for the bus to which the agents are connected. Thus, an arbiter corresponding to each... |
| US-6,633,936 |
Adaptive retry mechanism An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more... |
| US-6,630,945 |
Graphics display system with graphics window control mechanism A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video... |
| US-6,630,856 |
High-speed bank select multiplexer latch A high-speed bank select multiplexer latch may be coupled to a pair of differential output nodes and configured to capture and retain an output on the pair of... |
| US-6,629,218 |
Out of order associative queue in two clock domains A memory controller may include a request queue for receiving transaction information (e.g. the address of the transaction) and a channel control circuit. A... |
| US-6,628,224 |
Distributed averaging analog to digital converter topology An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in... |
| US-6,628,218 |
Method and apparatus for mismatched shaping of an oversampled converter Methods and apparatuses for spectrally shaping mismatch errors in a multi-bit digital to analog converter (DAC). In an embodiment, the multi-bit DAC is... |
| US-6,628,149 |
Sub-micron high input voltage tolerant input output (I/O) circuit A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the... |
| US-6,625,685 |
Memory controller with programmable configuration A memory controller provides programmable flexibility, via one or more configuration registers, for the configuration of the memory. The memory may be optimized... |
| US-6,625,459 |
Method and apparatus for efficient determination of channel estimate and
baud frequency offset estimate A method and apparatus for obtaining a channel estimate and a baud frequency offset estimate for a communications channel in a communications system. The... |
| US-6,624,819 |
Method and system for providing a flexible and efficient processor for use
in a graphics processing system A method and system for processing graphics data in a computer system are disclosed. The method and system including providing a general-purpose processor and... |
| US-6,624,699 |
Current-controlled CMOS wideband data amplifier circuits Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance... |
| US-6,621,675 |
High bandwidth, high PSRR, low dropout voltage regulator A voltage regulator may include one or more features for generating high PSRR. For example, source follower devices may be included in the voltage regulator for... |
| US-6,621,362 |
Varactor based differential VCO band switching Method and circuitry for implementing VCOs with improved frequency band switching use differentially-coupled varactors to implement the different frequency... |
| US-6,621,350 |
Switched supply for operational amplifier There is provided a circuit and method for providing a supply voltage to an operational amplifier. A switch has a plurality of inputs connected to a respective... |
| US-6,618,440 |
Burst mode memory fetches when decoding compressed image data An image data decompression apparatus for decoding blocks of motion compensated non-intra coded data uses a memory (14) storing reference picture data. A... |
| US-6,618,302 |
Memory architecture with single-port cell and dual-port (read and write)
functionality A single-port hierarchical memory structure including memory modules having memory cells; hierarchically-coupled local and global sense amplifiers; ... |
| US-6,614,768 |
Enhanced mobility and address resolution in a wireless premises based
network A mobile customer service station operating within a wireless multi-hop communication network includes a console on a wheeled chassis. The console carries and... |
| US-6,614,371 |
Synchronous data serialization circuit In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first... |
| US-6,611,568 |
Variable rate modulator Clock signals and digital data signals at a variable frequency are introduced to the input of a FIFO and are passed from the FIFO at a second (or intermediate)... |
| US-6,611,465 |
Diffusion replica delay circuit A diffusion replica delay circuit is included in a device with a device capacitance and operational characteristics. A diffusion replica capacitor, coupled to... |
| US-6,608,630 |
Graphics display system with line buffer control scheme A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video... |
| US-6,608,603 |
Active impedance matching in communications systems A signal sensing module senses an RF signal and produces one or more secondary signals representative of the RF signal. An impedance matching control module... |
| US-6,608,536 |
Constant impedance filter A constant impedance filter maintains a constant input impedance for frequencies that are both inside the filter passband and outside the filter passband. The... |
| US-6,608,527 |
Adaptive radio transceiver with low noise amplification An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local... |
| US-6,608,519 |
Methods and systems for limiting supply bounce Methods and systems for limiting power supply and ground bounce enables control of the output current drive dependent on the changes in supply (VDD and GND)... |
| US-6,606,352 |
Method and apparatus for converting between byte lengths and burdened burst
lengths in a high speed modem Requests are processed to transmit data packets upstream from a cable modem to a cable headend in a manner that minimizes the use of CPU operations and/or memory... |
| US-6,603,712 |
High precision delay measurement circuit A high-precision delay measurement circuit delivers exceptionally accurate time measurement, for example, a half-gate delay. The high-precision delay measurement... |
| US-6,603,417 |
CMOS DAC with high impedance differential current drivers High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes... |
| US-6,601,157 |
Register addressing There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first... |
| US-6,600,677 |
Memory circuit capable of simultaneous writing and refreshing on the same
column and a memory cell for... A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three ... |
| US-6,598,205 |
Memory-based shuffle-exchange traceback for gigabit ethernet transceiver A decoder having a memory structure which receives and stores potential symbols, with each of the potential symbols having a unique pointer associated therewith.... |
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