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Patent # Description
US-6,597,217 Low power, charge injection compensated charge pump
A charge pump includes at least one switching transistor for switching current on or off in response to an up or down signal, a pair of transistors (one coupled...
US-6,597,216 Apparatus and method for delay matching of full and divided clock signals
A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference...
US-6,597,211 Clock divider circuit producing 0.degree. and 90.degree. outputs with a 50% duty cycle
A clock divider circuit producing 0.degree. and 90.degree. outputs with a 50% duty cycle is provided. In one embodiment, the clock divider circuit may include a...
US-6,597,164 Test bus circuit and associated method
An on-chip test bus circuit for testing a plurality of circuits and an associated method. The test bus circuit consists of a test bus and a plurality of...
US-6,594,304 Adaptive configurable class-A/class-B transmit DAC for transceiver emission and power consumption control
A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications....
US-6,591,357 Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements
A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be...
US-6,591,091 System and method for coarse/fine PLL adjustment
An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front...
US-6,591,013 Switching between decoded image channels
An image data decoding system (2) is described in which a stream of compressed image data (1) corresponding to a plurality of image channels (ChA, ChB, ChC) each...
US-6,587,321 Methods and systems for improving ESD clamp response time
The present invention relates to electrostatic discharge (ESD) protection and, more particularly, to methods and systems for improving response times of ESD...
US-6,586,996 Method and system for producing a drive signal for a current steering amplifier
Provided is a method and system for producing a drive signal for a current steering amplifier. An exemplary method comprises receiving a supply voltage signal...
US-6,586,292 Guard mesh for noise isolation in highly integrated circuits
A methodology of creating integrated circuits with improved noise isolation is presented. The circuitry of an integrated circuits is separated into noise...
US-6,583,747 Subranging analog to digital converter with multi-phase clock timing
An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a...
US-6,583,675 Apparatus and method for phase lock loop gain control using unit current sources
A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel...
US-6,580,328 Lock detector for phase locked loops
A detector circuit for determining whether synchronization lock has been optimally achieved in feedback-type control systems. The detector circuit evaluates an...
US-6,580,156 Integrated fuse with regions of different doping within the fuse neck
An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The...
US-6,578,135 Method and apparatus for performing addressing operations in a superscalar superpipelined processor
A method and apparatus for improving the performance of a superscalar, superpipelined processor by identifying and processing instructions for performing...
US-6,577,261 Method and apparatus for mismatched shaping of an oversampled converter
Methods and apparatuses for spectrally shaping mismatch errors in a multi-bit digital to analog converter (DAC). In an embodiment, a range signal is produced...
US-6,577,257 Methods and systems for digital dither
Methods and systems for applying digital dither includes methods and systems for applying digital dither in data converters, such as, for example, delta-sigma...
US-6,577,184 Switched-capacitor, common-mode feedback circuit for a differential amplifier without tail current
Provided is a switched capacitor feedback circuit including two or more input ports configured to receive a corresponding a number of input signals and at least...
US-6,574,708 Source controlled cache allocation
A cache is coupled to receive an access which includes a cache allocate indication. If the access is a miss in the cache, the cache either allocates a cache...
US-6,574,136 Reduced leakage memory cell
A random access memory cell (10) includes a first conductor line (12) and a second conductor line (14). A native device (16) is arranged to store charge. A high...
US-6,573,905 Video and graphics system with parallel processing of graphics windows
A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple...
US-6,573,853 High speed analog to digital converter
An analog to digital converter includes a reference ladder, a track-and-hold amplifier tracking an input signal with its output signal during the phase...
US-6,573,851 Offset compensated comparing amplifier
A system and method for converting an analog input signal to a N-bit digital output signal. The invention comprises generating a plurality of reference voltage...
US-6,571,321 Read exclusive for fast, simple invalidate
An agent, in response to a write to a shared block, is configured to initiate a read exclusive transaction on an interface on which the agent communicates....
US-6,571,317 Replacement data error detector
A cache includes an error circuit for detecting errors in the replacement data. If an error is detected, the cache may update the replacement data to eliminate...
US-6,571,181 System and method for detecting a device requiring power
A system and technique for detecting a device that requires power is implemented with a power detection station. The power detection system includes a detector...
US-6,570,942 Multi-mode variable rate digital cable receiver
Carrier signals modulated by information (video and/or data) signals are received through a cable and are converted to modulated signals at an intermediate...
US-6,570,579 Graphics display system
A graphics integrated circuit is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input,...
US-6,570,448 System and method for a startup circuit for a differential CMOS amplifier
A system is provided for correcting start-up deficiencies in an amplifier. The system includes a comparing device configured to (i) receive a second circuit node...
US-6,570,417 Frequency dividing circuit
A frequency dividing circuit divides a master clock frequency by a non-integer factor to provide an output clock signal whose frequency is equal to the frequency...
US-6,570,403 Quantized queue length arbiter
A queue length arbiter system provides for selecting from a plurality of N queues requiring access to a resource. The system includes: an arbitration circuit;...
US-6,567,417 Frame forwarding in a switch fabric
A method of forwarding data in a network switch fabric is disclosed. An incoming data packet is received at a first port of the fabric and a first packet...
US-6,566,971 Method and circuitry for implementing a differentially tuned varactor-inductor oscillator
The present invention generally relates to voltage-controlled oscillators. More specifically, the present invention relates to method and circuitry for...
US-6,566,970 High-speed, high PSRR, wide operating range voltage controlled oscillator
A VCO for a PLL may include a ring oscillator having a power supply controlled in response to the VCO's control voltage input and an inverter having an input...
US-6,566,968 Oscillator having multi-phase complementary outputs
An oscillator having multi-phase complementary outputs comprises a first plurality of single ended amplifiers connected in series to form an input and an output...
US-6,566,957 Methods and systems for a MOSFET-bipolar complimentary symmetry driver with local feedback for bias stabilization
A SLIC assembly includes high voltage operational amplifiers (op amps) and low voltage op amps. The high voltage op amps are used to drive ring and tip signals...
US-6,566,940 Method and apparatus for frequency shift-keying demodulation and applications thereof
A method and apparatus for frequency shift-keying (FSK) demodulation includes processing that begins by generating a charge signal, a data acquisition signal,...
US-6,563,392 Varactor folding technique for phase noise reduction in electronic oscillators
A varactor folding technique reduces noise in controllable electronic oscillators through the use of a series of varactors having relatively small capacitance. A...
US-6,563,361 Method and apparatus for a limiting amplifier with precise output limits
A circuit and a method for limiting a voltage to a specified value (e.g., a rail voltage) without clipping thereby includes a pair of MOSFETs that turn on when a...
US-6,563,333 Dynamic register with IDDQ testing capability
The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating...
US-6,560,449 Image-rejection I/Q demodulators
In a communications receiver for quadrature demodulation, a feedback technique for reducing the image response of the receiver. The communications receiver...
US-6,560,229 Network switching architecture with multiple table synchronization, and forwarding of both IP and IPX packets
A network switch for network communications includes a first data port interface. The first data port interface supports a plurality of data ports transmitting...
US-6,559,685 Regenerative signal level converter
Method and circuitry for converting a differential logic signal to a single-ended logic signal that minimize delay. In specific embodiments differential logic...
US-6,556,993 Method and system for providing a hardware sort in a graphics system
A system and method for providing a sort in a computer system is disclosed. The sort is based on a plurality of values of a key. Each of the plurality of items...
US-6,556,059 High speed flip-flop
A bistable device has first and second complementary input terminals and first and second bistable states that are determined by the polarity of the signal...
US-6,553,479 Local control of multiple context processing elements with major contexts and minor contexts
A method and apparatus for providing local control of processing elements in a network of multiple context processing element are provided. A multiple context...
US-6,553,063 Constellation-multiplexed transmitter and receiver
A device of dynamic communication of information allows, on the average, non-integer bits per symbol transmission, using a compact code set or a partial response...
US-6,549,766 System and method for on-chip filter tuning
An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front...
US-6,549,599 Stable phase locked loop having separated pole
A phase locked loop circuit having a loop filter including a variable resistance for normal loop operation and for fast acquisition has improved stability by...
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