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Patent # Description
US-6,549,599 Stable phase locked loop having separated pole
A phase locked loop circuit having a loop filter including a variable resistance for normal loop operation and for fast acquisition has improved stability by...
US-6,549,587 Voice and data exchange over a packet based network with timing recovery
A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a...
US-6,546,520 Generalized convolutional interleaver/deinterleaver
A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their...
US-6,542,043 All PMOS fully differential voltage controlled oscillator
All PMOS (p channel metal oxide semiconductor) fully differential voltage controlled oscillator (VCO). A fully differential implementation within the present...
US-6,539,516 Forward error corrector
A method for decoding an algebraic-coded message including determining a discrepancy indicator; determining an error locator polynomial according to a modified...
US-6,538,943 Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low...
A ROM or other memory may include two or more partitions and a precharge circuit. Each of the partitions may be coupled to separate sets of output conductors, to...
US-6,538,656 Video and graphics system with a data transport processor
A video and graphics system uses multiple transport processors to receive compressed data streams to perform PID and section filtering as well as DVB and DES...
US-6,538,508 Programmable gain amplifier with glitch minimization
A programmable gain amplifier (PGA) has an amplifier and a variable resistor that is connected to the output of the amplifier. The variable resistor includes a...
US-6,535,510 Switch fabric with path redundancy
A method of forwarding data in a network switch fabric is disclosed. An incoming data packet is received at a first port of the fabric and a first packet...
US-6,535,036 Conditional clock buffer circuit
A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a...
US-6,535,025 Sense amplifier with offset cancellation and charge-share limited swing drivers
A sense amplifier adapted to sense an input signal on global bitlines, having an amplifier offset cancellation network and an offset equalization network. The...
US-6,531,973 Sigma-delta digital-to-analog converter
The present invention is directed to a sigma-delta digital to analog converted (DAC) including a digital-sigma delta modulator, a decimation filter, and a...
US-6,531,923 Low voltage input current mirror circuit and method
A low voltage current mirror circuit (also referred to as a bias circuit) for establishing a plurality of bias voltages from an input current supplied to an...
US-6,531,915 Biasing scheme for low supply headroom applications
Methods and apparatus for improving the current matching within current mirror circuits in applications such as low voltage integrated circuits. Embodiments of...
US-6,530,015 Accessing a test condition for multiple sub-operations using a test register
A method and system of executing computer instructions is described. Each instruction defines first and second operands and an operation to be carried out on...
US-6,530,012 Setting condition values in a computer
A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described....
US-6,529,935 Graphics display system with unified memory architecture
A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video...
US-6,529,395 Content addressable memory cell techniques
A content addressable memory cell (10) includes a circuit (20) operating from a predetermined supply voltage (VDD) for storing a first bit of data at a first...
US-6,529,058 Apparatus and method for obtaining stable delays for clock signals
A circuit and method for obtaining a stable delay for a clock signal comprises a current source to generate a constant current having a first value; first and...
US-6,526,498 Method and apparatus for retiming in a network of multiple context processing elements
A method and an apparatus for retiming in a network of multiple context processing elements are provided. A programmable delay element is configured to...
US-6,526,483 Page open hint in transactions
A system including an agent and a memory controller, in which the agent may initiate transactions targeting a memory to which the memory controller is coupled...
US-6,526,113 GM cell based control loops
Various circuit techniques employ a transconductance (gm) cell in control loops to implement circuits such as phase locked loops and delay locked loops that are...
US-6,525,955 Memory cell with fuse element
The present invention relates to a one-time programmable memory cell and a method of setting a state for a one-time programmable memory cell. The memory cell...
US-6,525,609 Large gain range, high linearity, low noise MOS VGA
An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides...
US-6,525,580 Circuit and method for multi-phase alignment
A method and circuit for adjusting clock pulse widths in a high speed sample and hold circuit. A single phase clock signal is input into a pulse discriminator...
US-6,525,571 Current-controlled CMOS circuits with inductive broadbanding
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3 MOS) logic with inductive broadbanding fabricated in...
US-6,522,279 Digital to analog converter with reduced ringing
Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and...
US-6,522,277 Circuit, system and method for performing dynamic element matching using bi-directional rotation within a data...
A circuit, system, and method are provided for imparting improved randomness into the selection of components or elements of a data converter, such as a D/A...
US-6,522,189 High-speed bank select multiplexer latch
A high-speed bank select multiplexer latch may be coupled to a pair of differential output nodes and configured to capture and retain an output on the pair of...
US-6,519,311 Overflow detector for FIFO
The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of...
US-6,519,204 Very small swing high performance CMOS static memory (multi-port register file) with power reducing column...
Devices and methods relating to a multi-port register file memory including a plurality of storage elements in columns are disclosed. The storage elements are...
US-6,518,892 Stopping criteria for iterative decoding
Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative...
US-6,518,805 Programmable divider with built-in programmable delay chain for high-speed/low power application
A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock...
US-6,512,416 Extended range variable gain amplifier
An extended range variable gain amplifier is described. The variable gain capability is achieved by replacing differential pair amplifiers having an input signal...
US-6,509,897 Method and system for providing implicit edge antialiasing
A method and system for providing antialiasing of a graphical image on a display from data describing at least one object is disclosed. The display includes a...
US-6,509,796 Variable transconductance variable gain amplifier utilizing a degenerated differential pair
Continuously tuning a transconductance. Coupling a degeneration resistance from a first source of a first transistor in a differential pair of transistors to a...
US-6,509,773 Phase interpolator device and method
A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at...
US-6,504,838 Voice and data exchange over a packet based network with fax relay spoofing
A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a...
US-6,504,420 Temperature compensation for internal inductor resistance
A compensation circuit compensates for the variation in the internal resistance of a multi-track inductor over temperature. The compensation circuit includes a...
US-6,504,408 Method and apparatus to ensure DLL locking at minimum delay
A method and apparatus to ensure DLL locking at a minimum delay is provided. In one embodiment, a DLL circuit includes a phase detector, a counter, a...
US-6,501,480 Graphics accelerator
A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics...
US-6,501,402 Digital-to-analogue converter using an array of current sources
A current source DAC has calibration of the current sources used for providing the analog output. There are two outputs, one of which provides the output current...
US-6,501,311 System and method for compensating for supply voltage induced signal delay mismatches
Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog...
US-6,498,823 Variable rate modulator
Digital data signals at a variable input frequency are converted by a numerically controlled oscillator and an interpolator to a signal at a fixed output...
US-6,496,067 Class AB voltage current convertor having multiple transconductance stages and its application to power amplifiers
A Class AB voltage-to-current converter includes a primary transconductance stage, secondary transconductance stage, and a biasing circuit. The biasing circuit...
US-6,493,409 Phase detectors in carrier recovery for offset QAM and VSB
Improved carrier recovery, symbol timing, and carrier phase tracking systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system...
US-6,492,844 Single-ended sense amplifier with sample-and-hold reference
A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal;...
US-6,486,887 Method and system for improving color quality of three-dimensional rendered images
A method and system for providing a graphical image on a display is disclosed. The image is provided from data describing at least one object. The display...
US-6,483,358 Low power, charge injection compensated charge pump
A charge pump includes at least one switching transistor for switching current on or off in response to an up or down signal, a pair of transistors (one coupled...
US-6,480,424 Compact analog-multiplexed global sense amplifier for RAMS
The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. The...
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