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Patent # Description
US-6,477,646 Security chip architecture and implementations for cryptography acceleration
An architecture and a method for a cryptography acceleration is disclosed that allows significant performance improvements without the use of external memory....
US-6,477,200 Multi-pair gigabit ethernet transceiver
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver...
US-6,477,199 Dynamic regulation of power consumption of a high-speed communication system
A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric...
US-6,473,607 Communication device with a self-calibrating sleep timer
The present invention provides for a system for operating a communication device (20) for reception of scheduled intermittent information messages (22) with a...
US-6,472,940 Gigabit ethernet transceiver with analog front end
Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain...
US-6,463,266 Radio frequency control for communications systems
The present invention provides for a system and method for improvement of radio transmitter and receiver frequency accuracy for a local radio communication unit...
US-6,463,041 Apparatus for, and method of, reducing noise in a communications system
A communication line having a plurality of twisted wire pairs connects a plurality of transmitters, one transmitter at each end of each twisted wire pair, with a...
US-6,459,746 Multi-pair gigabit ethernet transceiver
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver...
US-6,459,730 Apparatus for, and method of, processing signals transmitted over a local area network
Digital signals provided by a repeater connected to a plurality of clients by unshielded twisted wire pairs, are converted to analog signals which become...
US-6,457,116 Method and apparatus for controlling contexts of multiple context processing elements in a network of multiple...
A method and apparatus for providing local control of processing elements in a network of multiple context processing element are provided. A multiple context...
US-6,456,552 Dynamic register with low clock rate testing capability
A method for refreshing data in a circuit element included in a dynamic register. A static loop is coupled to the circuit element as a feedback path from the...
US-6,456,284 Graphics processor, system and method for generating screen pixels in raster order utilizing a single interpolator
A system and method for generating a graphical display from data describing at least one three-dimensional object is disclosed. The system method and system...
US-6,456,118 Decoder circuit
A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first...
US-6,449,701 Out of order associative queue in two clock domains
A memory controller may include a request queue for receiving transaction information (e.g. the address of the transaction) and a channel control circuit. A...
US-6,449,271 System for and method of, providing a header and a trailer in data packets
A header substituted for preamble nibbles by an individual one of the originating devices in a plurality, and an individual one of the ports in such originating...
US-6,445,731 Method and apparatus for reducing signal processing requirements for transmitting packet-based data with a modem
A modem and method for operating same. A receiver circuit of the modem is coupled to receive a continuous analog signal from a communication channel. This analog...
US-6,445,039 System and method for ESD Protection
An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front...
US-RE37,826 Ethernet system
Four (4) unshielded twisted pairs of wires connect a hub and a computer in an Ethernet system: one (1) pair for transmission only, another for reception only and...
US-6,441,660 High speed, wide bandwidth phase locked loop
A PLL may include a voltage regulator for providing a regulated voltage to one or more PLL components (e.g. a charge pump, a voltage controlled oscillator,...
US-6,441,655 Frequency division/multiplication with jitter minimization
A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency...
US-6,438,164 Technique for minimizing decision feedback equalizer wordlength in the presence of a DC component
A system for reducing the complexity of an adaptive decision feedback equalizer, for use in connection with a dual-mode QAM/VSB receiver system is disclosed. QAM...
US-6,437,652 Apparatus and method for reducing phase noise in oscillator circuits
A resonant oscillator circuit includes an active device and a resonator that causes the active device to oscillate at a resonant frequency of the resonator. The...
US-6,437,620 Circuit and method for multi-phase alignment
A method and circuit for adjusting clock pulse widths in a high speed sample and hold circuit. A single phase clock signal is input into a pulse discriminator...
US-6,430,188 Unified table for L2, L3, L4, switching and filtering
A network switch for network communications, wherein the network switch includes at least one data port interface supporting a plurality of data ports...
US-6,430,099 Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low...
A ROM or other memory may include two or more partitions and a precharge circuit. Each of the partitions may be coupled to separate sets of output conductors, to...
US-6,430,098 Transparent continuous refresh RAM cell architecture
A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three ...
US-6,426,680 System and method for narrow band PLL tuning
An integrated VCO having an improved tuning range over process and temperature variations. There is therefore provided in a present embodiment of the invention...
US-6,424,194 Current-controlled CMOS logic family
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3 MOS) logic fabricated in conventional CMOS process...
US-6,424,190 Apparatus and method for delay matching of full and divided clock signals
A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference...
US-6,424,177 Universal single-ended parallel bus
A high speed data communication system uses a single-ended bus architecture with a reference signal extracted from a differential periodic signal that is...
US-6,424,169 Active termination network
An active termination for a transmission line comprising a reference impedance, a terminating impedance and a control circuit. The reference and terminating...
US-6,421,396 Variable rate modulator
Clock signals and digital data signals at a variable frequency are introduced to the input of a FIFO and are passed from the FIFO at a second (or intermediate)...
US-6,420,901 Quantized queue length arbiter
A queue length arbiter system provides for selecting from a plurality of N queues requiring access to a resource. The system includes: an arbitration circuit;...
US-6,418,221 Signal coupler using low voltage filtering
A signal coupler is provided which decreases the number of discreet elements required to provide low pass filtering for the plain old telephone service (POTS)....
US-6,417,737 Adaptive radio transceiver with low noise amplification
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local...
US-6,417,697 Circuit technique for high speed low power data transfer bus
A high speed low power data transfer bus circuit that reduces bus power consumption by imposing a limited, controlled voltage swing on the associated data bus....
US-6,414,952 Virtual gateway system and method
Existing (already installed) plain old telephone service (POTS) wiring at a customer premises is used as the wiring infrastructure for a local area network and...
US-6,414,899 Limited swing driver circuit
A limited swing driver with a pass transistor coupled between a memory cell and an associated bitline; an inverter, its output coupled to the gate of the pass...
US-6,414,618 Digital to analog converter with reduced ringing
Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and...
US-6,414,557 High noise rejection voltage-controlled ring oscillator architecture
A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring...
US-6,411,659 Timing recovery using the pilot signal in high definition TV
Improved carrier recovery and symbol timing systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system is disclosed. Carrier and...
US-6,411,647 Fully integrated ethernet transmitter architecture with interpolating filtering
A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications....
US-6,411,557 Memory architecture with single-port cell and dual-port (read and write) functionality
A single-port hierarchical memory structure including memory modules having memory cells; hierarchically-coupled local and global sense amplifiers; ...
US-6,411,152 Conditional clock buffer circuit
A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a...
US-6,411,117 Dynamic register with IDDQ testing capability
A method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage during a steady...
US-6,408,349 Adjustable elasticity fifo buffer have a number of storage cells equal to a frequency offset times a number of...
The drift between a write pointer and a read pointer processing packets of data through a FIFO buffer is compensated for by adjusting the start of the read...
US-6,407,692 Analog to digital converter
The output of each cell in an A-D converter on an IC chip is dependent upon the relative values of an input voltage and an individual one of progressive...
US-6,407,688 CMOS DAC with high impedance differential current drivers
High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes...
US-6,404,293 Adaptive radio transceiver with a local oscillator
An oscillator circuit is disclosed which includes an oscillator to generate a first signal having a first frequency, a second oscillation source to generate a...
US-6,400,228 Switched supply for operational amplifier
There is provided a circuit and method for providing a supply voltage to an operational amplifier. A switch has a plurality of inputs connected to a respective...
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