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Patent # Description
US-8,063,712 Method and system for voltage controlled oscillator impedance control to optimize performance, efficiency, and...
Methods and systems for VCO impedance control to optimize performance, efficiency, and power consumption are disclosed and may include selectively coupling one...
US-8,063,706 Cascode CMOS RF power amplifier with programmable feedback cascode bias under multiple supply voltages
A Radio Frequency (RF) cascode power amplifier operates with differing battery supply voltages. A transconductance stage has a transistor with an RF signal...
US-8,062,133 Positioning within a video gaming environment using RF signals
The position of a mobile gaming object within a video gaming environment is determined using at least one combined Radio Frequency (RF) signal. Each combined RF...
US-8,060,674 Systems and methods for data storage devices and controllers
An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete...
US-8,060,050 Method and system for analog and digital RF receiver interface
In a wireless device, a method and system for a baseband receiver interface including analog and digital components are provided. An analog or a digital...
US-8,060,029 Antenna with resonator grid and methods for use therewith
An antenna includes a planar antenna section. A resonator grid includes a plurality of resonators in a planar array to electromagnetically enhance the...
US-8,059,740 WLAN transmitter having high data throughput
A wireless local area network (WLAN) transmitter includes a baseband processing module and a plurality of radio frequency (RF) transmitters. The baseband...
US-8,059,706 Method and system for transmission and/or reception of signals utilizing a delay circuit and DDFS
Aspects of a method and system for transmission and/or reception of signals utilizing a delay circuit and a DDFS are provided. In this regard, a first signal...
US-8,059,674 Video processing system
The present invention is directed to a system for demultiplexing video signals that have been combined using a time division multiplexing approach. The system...
US-8,059,648 System and method for isolating network clients
A network device includes at least one first network port, at least one second network port, a MUX unit and a switching unit. The MUX unit is connected to the...
US-8,059,537 Quality of service support in a media exchange network
Certain aspects of the invention for controlling transfer of media content in a communication network may comprise the step of receiving an input specifying at...
US-8,058,928 Operational amplifier for an active pixel sensor
The present invention includes operational amplifier for an active pixel sensor that detects optical energy and generates an analog output that is proportional...
US-8,055,990 Method and system for error detection for improving data integrity in protocol offloading
Aspects of a method and system are provided for error detection for improving data integrity in protocol offloading. Aspects of the invention may enable...
US-8,055,895 Data path security processing
Methods and associated systems provide secured data transmission over a data network. A security device provides security processing in the data path of a...
US-8,055,313 Mobile communication device with low power receiver for signal detection
A mobile communication device with a low power receiver for signal detection and a method for utilizing a low power receiver for signal detection in a mobile...
US-8,055,207 RF receiver with fast baseband switching
A receiver includes a plurality of RF receiver modules, a plurality of analog baseband sections, a plurality of analog to digital conversion sections, and a...
US-8,054,856 Method for synchronizing voice traffic with minimum latency in a communications network
A supervisory communications node monitors and controls communications with a plurality of remote devices throughout a widely distributed network. A method is...
US-8,054,222 Method and apparatus for combining measurements and determining clock offsets between different global...
Method and apparatus for processing satellite signals from a first satellite navigation system and a second satellite navigation system is described. In one...
US-8,051,463 Method and system for distribution of configuration information among access points in a wireless local area...
Aspects of a method and system for distribution of configuration information among access points (AP) in a WLAN across a distribution system (DS) are presented....
US-8,051,233 Method and system for addressing a plurality of ethernet controllers integrated into a single chip which...
A method for processing network data is disclosed and may include receiving data via a single bus interface to which each of a plurality of Ethernet controllers...
US-8,051,160 Method and apparatus for a network hub to diagnose network operation and broadcast information to a remote host...
A network hub in a communication network that acts as a server to network clients to push, or transmit, information regarding the state of local and remote...
US-8,050,647 Method and system for frequency feedback adjustment in digital receivers
In RF transceivers, a method and a system for a frequency feedback adjustment in digital receivers are provided. A DC offset may result from the difference in...
US-8,050,636 Apparatus and method for generating RF without harmonic interference
A transmitter capable of operating according to a first standard that does not interfere with a nearby frequency generator operating according to a second...
US-8,050,412 Scaling adjustment to enhance stereo separation
A demodulator (10) converts television signals to video baseband signals and audio baseband signals including stereo signals representing a right channel signal...
US-8,050,373 Phase interpolator based transmission clock control
A system and method is provided for phase interpolator based transmission clock control. The system includes a transmitter having a phase interpolator coupled...
US-8,050,330 Multiple time-base clock for processing multiple satellite signals
An integrated receiver with multiple, independently synchronized clock signals for multiple channel transport stream decoding and delivery substantially...
US-8,050,237 Synchronization channel noise power estimation
Apparatus and method to process a pilot channel and a synchronization channel to obtain a combined noise estimate of the pilot channel and the synchronization...
US-8,050,173 Dynamic precision for datapath modules
A system and method for dynamically reducing the precision of datapath modules within an FFT unit without adversely affecting the demodulation of an orthogonal...
US-8,050,076 One-time programmable memory cell with shiftable threshold voltage transistor
According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor...
US-8,049,676 Planer antenna structure
A planer antenna structure includes a first planer antenna and a second planer antenna. The first planer antenna has a first axial orientation and a conductive...
US-8,049,568 Feedback-based linearization of voltage controlled oscillator
Embodiments of the present invention enable a feedback-based VCO linearization technique. Embodiments include a frequency locked loop formed by feeding back a...
US-8,049,302 On-chip capacitor structure with adjustable capacitance
At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be...
US-8,049,278 ESD protection for high voltage applications
An ESD device includes a low doped well connected to a first contact and a diffusion area connected to a second contact. A substrate between the low doped well...
US-8,048,765 Method for fabricating a MOS transistor with source/well heterojunction and related structure
According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The...
US-8,046,662 Method and system for decoding control data in GSM-based systems using inherent redundancy
A method and system for decoding control data in GSM-based systems using inherent redundancy and physical constraints are presented. At least one estimated...
US-8,046,621 Method and system for generation of signals up to extremely high frequencies using a delay block
Aspects of a method and system for generation of signals up to extremely high frequency using a delay block are provided. In this regard, a first signal may be...
US-8,046,568 Microprocessor with integrated high speed memory
The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values...
US-8,046,510 Physical layer device having a SERDES pass through mode
A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second...
US-8,046,482 System and method for managing multiple stack environments
Systems and methods that manage multiple stack environments are provided. In one example, a system may include, for example, a first protocol processing stack,...
US-8,045,932 Double search user group selection scheme with range reduction for FDD multiuser MIMO downlink transmission...
Aspects of a double search user group selection scheme with range reduction for FDD multiuser MIMO downlink transmission with finite-rate channel state...
US-8,045,716 System and method for the concealment of device input parameters
A system and method for concealing input parameters that are being loaded into a device. In one embodiment, the system provides a transformed interface, in...
US-8,045,707 System and method for securing data
Systems and systems that protect data are provided. In one embodiment, a system may include, for example, a memory and a processor. The memory may store, for...
US-8,045,674 Method and system for use of TSPC logic for high-speed multi-modulus divider in PLL
Aspects of a method and system for use of true single phase clock (TSPC) logic for a high-speed multi-modulus divider in a phase locked loop (PLL) are provided....
US-8,045,651 Method and system for redundancy-based decoding in 8-PSK GSM systems
Aspects of a method and system for redundancy-based decoding in 8-PSK GSM systems are provided. A burst process may utilize a gradient search equalization...
US-8,045,066 Fully integrated tuner architecture
An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front...
US-8,044,747 Capacitor coupled Ethernet
A system and method for enabling power applications over a single conductor pair. In one embodiment, data transformers are coupled to a single conductor pair...
US-8,041,853 Adjustable elasticity FIFO buffer with preload value having a number of storage cells equal to frequency offset...
A method of processing a data stream through a buffer is performed in accordance with a write clock and a read clock. The buffer has a plurality of sequentially...
US-8,041,827 Interoperability of a network interface protocol with an internet interface protocol
A method for interoperability of a network interface protocol with an Internet interface protocol begins by receiving a scan channel request of a plurality of...
US-8,041,562 Constrained and controlled decoding after packet loss
A technique is described herein for reducing audible artifacts in an audio output signal generated by decoding a received frame in a series of frames...
US-8,041,404 Multiple network wake-up
A system and method for managing messaging in a mobile communication system (e.g., having power-save capability) in a multiple network environment. For example,...
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