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Scalable synchronous packet transmit scheduler
A baseband controller system creates and maintains a schedule of synchronized events and reviews the schedule as a part of determining whether to initiate a...
Method and system for decimating an indexed set of data elements
A method and system are disclosed for decimating an indexed set of data elements to generate a decimated set of data elements. The indexed set of data elements...
Variable gain amplifier and method for achieving variable gain
amplification with high bandwidth and linearity
Various example embodiments are disclosed. According to one example embodiment, a high bandwidth, fine granularity variable gain amplifier ("VGA") may comprise...
Combination of analog and digital feedback for adaptive slew rate control
An apparatus for scaling a load device with frequency in a phase interpolator can include an analog loop and a digital loop. The load device of the phase...
Combined LDPC (low density parity check) encoder and syndrome checker
Combined LDPC (Low Density Parity Check) encoder and syndrome checker. A novel approach is presented by which the encoding processing and at least a portion of...
Apparatus and method for real time tracking using a quadrature interface
An apparatus for tracking a real time clock comprising a delay element for receiving a first clock signal and providing a second delayed clock signal, a...
Protocol and interface between a LAN on motherboard (LOM) and a powered
device (PD) for a personal computing...
A Power-over-Ethernet (PoE) communication system dynamically provides power and data communications over a communications link. In a computing environment made...
System and method for interrupt abstraction
A system and method that abstracts an interrupt from a group of interrupts, which may occur in a module, to call another module. Abstracting one interrupt from a...
Bridges performing remote reads and writes as uncacheable coherent
A system for managing data in multiple data processing devices using common data paths. Embodiments of the invention comprise a first data processing system...
Pitch extraction methods and systems for speech coding using sub-multiple
time lag extraction
A method of determining a pitch period of an audio signal using a correlation-based signal derived from the audio signal. The correlation-based signal includes...
Single chip multimode baseband processing circuitry with a shared radio
A multimode communication integrated circuit comprising baseband processing circuitry with a shared radio interface. Various aspects of the present invention may...
Hybrid on-chip-off-chip transformer
A hybrid on-chip-off-chip transformer includes an off-chip winding section and an on-chip winding section. The off-chip winding section is coupled to produce a...
A method and apparatus are disclosed for efficiently de-scrambling one or more bytes of data according to DSL standards on a processor. This is achieved by...
Inter-device adaptable interfacing clock skewing
Inter-device adaptable interfacing clock skewing. The invention is operable in either one of both of a transmit mode and a receive mode to perform skewing of a...
Video encoding and video/audio/data multiplexing device
The present invention provides a buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides...
Communications signal transcoder
Communications signal transcoder. A solution is provided to transcode a signal from a first signal type to a second signal type to ensure proper interfacing...
Channel estimation for a high-speed data packet access rake receiver
An HSDPA rake receiver has a plurality of rake fingers. Different channels may experience different spreading factors. The channel estimate (CE) and the CE delay...
Signaling format for WLANS
A method for wireless communication begins by determining whether legacy devices are within a proximal region of the wireless communication. The method...
Method, system, and computer program product for high performance bonding
A method, system, and computer program product for receiving and resequencing a plurality of data segments received on a plurality of channels of a bonding...
Switching network employing a user challenge mechanism to counter denial
of service attacks
A communication infrastructure includes an intermediate routing node that routes a plurality of packets between a source device and a plurality of destination...
Synchronized UWB piconets for simultaneously operating piconet performance
Synchronized UWB piconets for SOP (Simultaneously Operating Piconet) performance. A common backbone (either wired or wireless) is employed that provides a common...
Double data rate-single data rate input block and method for using same
Disclosed is a double data rate (DDR) input block comprising first and second input registers corresponding to a DDR input of the DDR input block. The first and...
Method for improving sequence detection performance by removing excess
A method leverages knowledge of the actual or ideal bit sequence to improve the performance of any sequence detector. This improved performance results by...
An audio/video separator provides a high-performance and cost-effective solution to analog TV reception with only one A/D converter and a minimum of analog IF...
BTSC pilot signal lock
An integrated digital BTSC encoder with an improved pilot signal generator substantially implemented on a single CMOS integrated circuit. By digitally generating...
System and method for static region detection in video processing
A system and method for processing video information are disclosed and may include calculating at least one pixel difference between at least one pixel in a...
Impedance transformer and applications thereof
An impedance transformer includes a first winding and a second winding. The first winding includes a first plurality of winding components, wherein each of the...
Enhanced polar modulator for transmitter
Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), a two point modulation topology is employed in which phase information passes through...
High-resolution low-interconnect phase rotator
High-resolution low-interconnect phase rotator. A signal may be generated having any desired phase (as determined by the step size employed). First and second...
Digital divider for low voltage LOGEN
Digital divider for low voltage LOGEN. LOGEN is a local oscillator generator. One implementation presented herein provides for a pseudo-complementary...
Voltage supply interface with current sensitivity and reduced series
A voltage supply interface provides both coarse and fine current control with reduced series resistance. The voltage supply interface has a segmented switch...
Integrated circuit with multiple independent power supply zones
An integrated circuit comprising multiple independent power supply zones at substantially the same voltage level and a method for utilizing such power supply...
Inductively coupled integrated circuit and methods for use therewith
A circuit includes a first integrated circuit or die having a first circuit and a first inductive interface. A second integrated circuit or die has a second...
Method and system for iSCSI boot in which an iSCSI client loads boot code
from a host bus adapter and/or...
Certain aspects of a method for iSCSI boot may include loading boot BIOS code from a host bus adapter or a network interface controller (NIC) by an iSCSI client...
Microprocessor with integrated high speed memory
A computer system with a processor architecture having more than one execution channel is described. The processor architecture contains at least one load/store...
Disk formatter and methods for use therewith
A disk formatter includes an address module for creating disk block address data corresponding to a disk sector of a disk drive. A sector write module initiates...
Method and system for rate adaptation
A media access controller to adapt a rate of an output signal to a rate of an output medium is provided. The media access controller includes a register...
Gain control in a multiple RF transceiver integrated circuit
A radio frequency (RF) transceiver integrated circuit (IC) includes a plurality of baseband Tx sections, a plurality of RF Tx sections, a plurality of RF Rx...
Method and system for stereo echo cancellation for VoIP communication
An exemplary embodiment of the present invention is directed toward a method and system for cancelling line echo in the presence of a known secondary audio...
Method and system for bandwidth calibration for a phase locked loop (PLL)
Aspects of a method and system for bandwidth calibration for a phase locked loop are presented. Aspects of the method may include generating one or more carrier...
Asymmetrical MIMO wireless communications
A method for asymmetrical MIMO wireless communication begins by determining a number of transmission antennas for the asymmetrical MIMO wireless communication....
System and method for fault tolerant TCP offload
Systems and methods that provide fault tolerant transmission control protocol (TCP) offloading are provided. In one example, a method that provides fault...
Fast flexible filter processor based architecture for a network device
A method of filtering data packets in a network device is disclosed. An incoming packet is received from a port and the incoming packet is inspected and packet...
Method and system for a gigabit Ethernet IP telephone chip with integrated
Methods and systems for processing Ethernet data are disclosed and may comprise receiving Ethernet data via a single gigabit Ethernet IP telephone chip. A secure...
Time multiplexing logic in physical design domain for multiple
An apparatus and method are provided to perform a time multiplexing logic in a module, are provided including identifying a driving flop and a receiving flop in...
Range checking content addressable memory array
A disclosed embodiment is a range checking CAM array comprising a plurality of words, where each of the plurality of words comprises a plurality of bound check...
Method and system for improving the appearance of deinterlaced chroma
Herein described is a system and method for improving the appearance of video by generating an improved 4:2:2 chroma. The system comprises a 4:2:2 to 4:2:0...
Graphics display system with anti-aliased text and graphics feature
A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video...
RF reception system and integrated circuit with programmable impedance
matching network and methods for use...
An integrated circuit includes an on-chip antenna interface, coupled to an off-chip antenna interface having at least one off-chip impedance matching component,...
Sub-micron high input voltage tolerant input output (I/O) circuit
A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the...